smmu_v3_transl.cc (14065:f925f90bda01) smmu_v3_transl.cc (14100:6ef1220dc6da)
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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600
601
602 // Establish stage 2 context first since
603 // Context Descriptors can be in IPA space.
604 if (tc.stage2Enable) {
605 tc.httb = ste.dw3.s2ttb << STE_S2TTB_SHIFT;
606 tc.vmid = ste.dw2.s2vmid;
607 tc.stage2TranslGranule = ste.dw2.s2tg;
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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600
601
602 // Establish stage 2 context first since
603 // Context Descriptors can be in IPA space.
604 if (tc.stage2Enable) {
605 tc.httb = ste.dw3.s2ttb << STE_S2TTB_SHIFT;
606 tc.vmid = ste.dw2.s2vmid;
607 tc.stage2TranslGranule = ste.dw2.s2tg;
608 tc.s2t0sz = ste.dw2.s2t0sz;
608 } else {
609 tc.httb = 0xdeadbeef;
610 tc.vmid = 0;
611 tc.stage2TranslGranule = TRANS_GRANULE_INVALID;
609 } else {
610 tc.httb = 0xdeadbeef;
611 tc.vmid = 0;
612 tc.stage2TranslGranule = TRANS_GRANULE_INVALID;
613 tc.s2t0sz = 0;
612 }
613
614
615 // Now fetch stage 1 config.
616 if (context.stage1Enable) {
617 ContextDescriptor cd;
618 doReadCD(yield, cd, ste, request.sid, request.ssid);
619
620 tc.ttb0 = cd.dw1.ttb0 << CD_TTB_SHIFT;
621 tc.ttb1 = cd.dw2.ttb1 << CD_TTB_SHIFT;
622 tc.asid = cd.dw0.asid;
623 tc.stage1TranslGranule = cd.dw0.tg0;
614 }
615
616
617 // Now fetch stage 1 config.
618 if (context.stage1Enable) {
619 ContextDescriptor cd;
620 doReadCD(yield, cd, ste, request.sid, request.ssid);
621
622 tc.ttb0 = cd.dw1.ttb0 << CD_TTB_SHIFT;
623 tc.ttb1 = cd.dw2.ttb1 << CD_TTB_SHIFT;
624 tc.asid = cd.dw0.asid;
625 tc.stage1TranslGranule = cd.dw0.tg0;
626 tc.t0sz = cd.dw0.t0sz;
624 } else {
625 tc.ttb0 = 0xcafebabe;
626 tc.ttb1 = 0xcafed00d;
627 tc.asid = 0;
628 tc.stage1TranslGranule = TRANS_GRANULE_INVALID;
627 } else {
628 tc.ttb0 = 0xcafebabe;
629 tc.ttb1 = 0xcafed00d;
630 tc.asid = 0;
631 tc.stage1TranslGranule = TRANS_GRANULE_INVALID;
632 tc.t0sz = 0;
629 }
630
631 return true;
632}
633
634void
635SMMUTranslationProcess::walkCacheLookup(
636 Yield &yield,

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870 smmu.getPageTableOps(context.stage1TranslGranule);
871
872 const WalkCache::Entry *walk_ep = NULL;
873 unsigned level;
874
875 // Level here is actually (level+1) so we can count down
876 // to 0 using unsigned int.
877 for (level = pt_ops->lastLevel() + 1;
633 }
634
635 return true;
636}
637
638void
639SMMUTranslationProcess::walkCacheLookup(
640 Yield &yield,

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874 smmu.getPageTableOps(context.stage1TranslGranule);
875
876 const WalkCache::Entry *walk_ep = NULL;
877 unsigned level;
878
879 // Level here is actually (level+1) so we can count down
880 // to 0 using unsigned int.
881 for (level = pt_ops->lastLevel() + 1;
878 level > pt_ops->firstLevel();
882 level > pt_ops->firstLevel(context.t0sz);
879 level--)
880 {
881 walkCacheLookup(yield, walk_ep, addr,
882 context.asid, context.vmid, 1, level-1);
883
884 if (walk_ep)
885 break;
886 }

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903 if (context.stage2Enable) {
904 TranslResult s2tr = translateStage2(yield, table_addr, false);
905 if (s2tr.fault != FAULT_NONE)
906 return s2tr;
907
908 table_addr = s2tr.addr;
909 }
910
883 level--)
884 {
885 walkCacheLookup(yield, walk_ep, addr,
886 context.asid, context.vmid, 1, level-1);
887
888 if (walk_ep)
889 break;
890 }

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907 if (context.stage2Enable) {
908 TranslResult s2tr = translateStage2(yield, table_addr, false);
909 if (s2tr.fault != FAULT_NONE)
910 return s2tr;
911
912 table_addr = s2tr.addr;
913 }
914
911 tr = walkStage1And2(yield, addr, pt_ops, pt_ops->firstLevel(),
915 tr = walkStage1And2(yield, addr, pt_ops,
916 pt_ops->firstLevel(context.t0sz),
912 table_addr);
913 }
914
915 if (tr.fault == FAULT_NONE)
916 DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
917
918 return tr;
919}

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944
945 return tr;
946 } else if (smmu.ipaCacheEnable) {
947 DPRINTF(SMMUv3, " IPACache miss ipa=%#x vmid=%#x\n",
948 addr, context.vmid);
949 }
950
951 const WalkCache::Entry *walk_ep = NULL;
917 table_addr);
918 }
919
920 if (tr.fault == FAULT_NONE)
921 DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
922
923 return tr;
924}

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949
950 return tr;
951 } else if (smmu.ipaCacheEnable) {
952 DPRINTF(SMMUv3, " IPACache miss ipa=%#x vmid=%#x\n",
953 addr, context.vmid);
954 }
955
956 const WalkCache::Entry *walk_ep = NULL;
952 unsigned level = pt_ops->firstLevel();
957 unsigned level = pt_ops->firstLevel(context.s2t0sz);
953
954 if (final_tr || smmu.walkCacheNonfinalEnable) {
955 // Level here is actually (level+1) so we can count down
956 // to 0 using unsigned int.
957 for (level = pt_ops->lastLevel() + 1;
958
959 if (final_tr || smmu.walkCacheNonfinalEnable) {
960 // Level here is actually (level+1) so we can count down
961 // to 0 using unsigned int.
962 for (level = pt_ops->lastLevel() + 1;
958 level > pt_ops->firstLevel();
963 level > pt_ops->firstLevel(context.s2t0sz);
959 level--)
960 {
961 walkCacheLookup(yield, walk_ep, addr,
962 0, context.vmid, 2, level-1);
963
964 if (walk_ep)
965 break;
966 }

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976 tr.addr = walk_ep->pa + (addr & ~walk_ep->vaMask);
977 tr.addrMask = walk_ep->vaMask;
978 tr.writable = walk_ep->permissions;
979 } else {
980 tr = walkStage2(yield, addr, final_tr, pt_ops,
981 level + 1, walk_ep->pa);
982 }
983 } else {
964 level--)
965 {
966 walkCacheLookup(yield, walk_ep, addr,
967 0, context.vmid, 2, level-1);
968
969 if (walk_ep)
970 break;
971 }

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981 tr.addr = walk_ep->pa + (addr & ~walk_ep->vaMask);
982 tr.addrMask = walk_ep->vaMask;
983 tr.writable = walk_ep->permissions;
984 } else {
985 tr = walkStage2(yield, addr, final_tr, pt_ops,
986 level + 1, walk_ep->pa);
987 }
988 } else {
984 tr = walkStage2(yield, addr, final_tr, pt_ops, pt_ops->firstLevel(),
989 tr = walkStage2(yield, addr, final_tr, pt_ops,
990 pt_ops->firstLevel(context.s2t0sz),
985 context.httb);
986 }
987
988 if (tr.fault == FAULT_NONE)
989 DPRINTF(SMMUv3, " Translated %saddr %#x to paddr %#x\n",
990 context.stage1Enable ? "ip" : "v", addr, tr.addr);
991
992 if (smmu.ipaCacheEnable) {

--- 468 unchanged lines hidden --- 		991 context.httb);
992 }
993
994 if (tr.fault == FAULT_NONE)
995 DPRINTF(SMMUv3, " Translated %saddr %#x to paddr %#x\n",
996 context.stage1Enable ? "ip" : "v", addr, tr.addr);
997
998 if (smmu.ipaCacheEnable) {

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