1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 req.isWrite = false;
74 req.isPrefetch = true;
75 req.isAtsRequest = false;
76 req.pkt = NULL;
77
78 return req;
79}
80
81void
82SMMUTranslationProcess::beginTransaction(const SMMUTranslRequest &req)
83{
84 request = req;
85
86 reinit();
87}
88

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1168SMMUTranslationProcess::issuePrefetch(Addr addr)
1169{
1170 if (!smmu.system.isTimingMode())
1171 return;
1172
1173 if (!ifc.prefetchEnable || ifc.xlateSlotsRemaining == 0)
1174 return;
1175
1176 ifc.xlateSlotsRemaining--;
1177
1178 std::string proc_name = csprintf("%sprf", name());
1179 SMMUTranslationProcess *proc =
1180 new SMMUTranslationProcess(proc_name, smmu, ifc);
1181
1182 proc->beginTransaction(
1183 SMMUTranslRequest::prefetch(addr, request.sid, request.ssid));
1184 proc->scheduleWakeup(smmu.clockEdge(Cycles(1)));
1185}

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1196 1;
1197
1198 doSemaphoreDown(yield, smmu.masterPortSem);
1199 doDelay(yield, Cycles(numMasterBeats));
1200 doSemaphoreUp(smmu.masterPortSem);
1201
1202
1203 smmu.translationTimeDist.sample(curTick() - recvTick);
1204 ifc.xlateSlotsRemaining++;
1205 if (!request.isAtsRequest && request.isWrite)
1206 ifc.wrBufSlotsRemaining +=
1207 (request.size + (ifc.portWidth-1)) / ifc.portWidth;
1208
1209 smmu.scheduleSlaveRetries();
1210
1211
1212 SMMUAction a;

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1244 a.delay = 0;
1245 yield(a);
1246 }
1247}
1248
1249void
1250SMMUTranslationProcess::completePrefetch(Yield &yield)
1251{
1252 ifc.xlateSlotsRemaining++;
1253
1254 SMMUAction a;
1255 a.type = ACTION_TERMINATE;
1256 a.pkt = NULL;
1257 a.ifc = &ifc;
1258 a.delay = 0;
1259 yield(a);
1260}
1261

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