1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
41#define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
42
43#include <list>
44
45#include "dev/arm/smmu_v3_caches.hh"
46#include "dev/arm/smmu_v3_defs.hh"
47#include "dev/arm/smmu_v3_events.hh"
48#include "dev/arm/smmu_v3_ports.hh"
49#include "dev/arm/smmu_v3_proc.hh"
50#include "mem/mem_object.hh"
51#include "params/SMMUv3SlaveInterface.hh"
52
53class SMMUTranslationProcess;
54class SMMUv3;
55class SMMUSlavePort;
56
57class SMMUv3SlaveInterface : public MemObject
58{
59 protected:
60 friend class SMMUTranslationProcess;
61
62 public:
63 SMMUv3 *smmu;
64 SMMUTLB* microTLB;
65 SMMUTLB* mainTLB;
66
67 const bool microTLBEnable;
68 const bool mainTLBEnable;
69
70 SMMUSemaphore slavePortSem;
71 SMMUSemaphore microTLBSem;
72 SMMUSemaphore mainTLBSem;
73
74 const Cycles microTLBLat;
75 const Cycles mainTLBLat;
76
77 SMMUSlavePort *slavePort;
78 SMMUATSSlavePort atsSlavePort;
79 SMMUATSMasterPort atsMasterPort;
80
81 // in bytes
82 const unsigned portWidth;
83
84 unsigned wrBufSlotsRemaining;
85 unsigned xlateSlotsRemaining;
| 1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
41#define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
42
43#include <list>
44
45#include "dev/arm/smmu_v3_caches.hh"
46#include "dev/arm/smmu_v3_defs.hh"
47#include "dev/arm/smmu_v3_events.hh"
48#include "dev/arm/smmu_v3_ports.hh"
49#include "dev/arm/smmu_v3_proc.hh"
50#include "mem/mem_object.hh"
51#include "params/SMMUv3SlaveInterface.hh"
52
53class SMMUTranslationProcess;
54class SMMUv3;
55class SMMUSlavePort;
56
57class SMMUv3SlaveInterface : public MemObject
58{
59 protected:
60 friend class SMMUTranslationProcess;
61
62 public:
63 SMMUv3 *smmu;
64 SMMUTLB* microTLB;
65 SMMUTLB* mainTLB;
66
67 const bool microTLBEnable;
68 const bool mainTLBEnable;
69
70 SMMUSemaphore slavePortSem;
71 SMMUSemaphore microTLBSem;
72 SMMUSemaphore mainTLBSem;
73
74 const Cycles microTLBLat;
75 const Cycles mainTLBLat;
76
77 SMMUSlavePort *slavePort;
78 SMMUATSSlavePort atsSlavePort;
79 SMMUATSMasterPort atsMasterPort;
80
81 // in bytes
82 const unsigned portWidth;
83
84 unsigned wrBufSlotsRemaining;
85 unsigned xlateSlotsRemaining;
|
86
87 const bool prefetchEnable;
88 const bool prefetchReserveLastWay;
89
90 std::list<SMMUTranslationProcess *> duplicateReqs;
91 SMMUSignal duplicateReqRemoved;
92
93 std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID];
94 std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
95 SMMUSignal dependentReqRemoved;
96
97 // Receiving translation requests from the master device
98 Tick recvAtomic(PacketPtr pkt);
99 bool recvTimingReq(PacketPtr pkt);
100 void schedTimingResp(PacketPtr pkt);
101
102 Tick atsSlaveRecvAtomic(PacketPtr pkt);
103 bool atsSlaveRecvTimingReq(PacketPtr pkt);
104 bool atsMasterRecvTimingResp(PacketPtr pkt);
105 void schedAtsTimingResp(PacketPtr pkt);
106
107 void scheduleDeviceRetry();
108 void sendDeviceRetry();
109 void atsSendDeviceRetry();
110
111 bool deviceNeedsRetry;
112 bool atsDeviceNeedsRetry;
113
114 SMMUDeviceRetryEvent sendDeviceRetryEvent;
115 EventWrapper<
116 SMMUv3SlaveInterface,
117 &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent;
118
119 Port& getPort(const std::string &name, PortID id) override;
120
121 public:
122 SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p);
123
124 ~SMMUv3SlaveInterface()
125 {
126 delete microTLB;
127 delete mainTLB;
128 }
129
130 const SMMUv3SlaveInterfaceParams *
131 params() const
132 {
133 return static_cast<const SMMUv3SlaveInterfaceParams *>(_params);
134 }
135
136 DrainState drain() override;
137
138 void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
139 void sendRange();
140};
141
142#endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */
| 87
88 const bool prefetchEnable;
89 const bool prefetchReserveLastWay;
90
91 std::list<SMMUTranslationProcess *> duplicateReqs;
92 SMMUSignal duplicateReqRemoved;
93
94 std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID];
95 std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
96 SMMUSignal dependentReqRemoved;
97
98 // Receiving translation requests from the master device
99 Tick recvAtomic(PacketPtr pkt);
100 bool recvTimingReq(PacketPtr pkt);
101 void schedTimingResp(PacketPtr pkt);
102
103 Tick atsSlaveRecvAtomic(PacketPtr pkt);
104 bool atsSlaveRecvTimingReq(PacketPtr pkt);
105 bool atsMasterRecvTimingResp(PacketPtr pkt);
106 void schedAtsTimingResp(PacketPtr pkt);
107
108 void scheduleDeviceRetry();
109 void sendDeviceRetry();
110 void atsSendDeviceRetry();
111
112 bool deviceNeedsRetry;
113 bool atsDeviceNeedsRetry;
114
115 SMMUDeviceRetryEvent sendDeviceRetryEvent;
116 EventWrapper<
117 SMMUv3SlaveInterface,
118 &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent;
119
120 Port& getPort(const std::string &name, PortID id) override;
121
122 public:
123 SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p);
124
125 ~SMMUv3SlaveInterface()
126 {
127 delete microTLB;
128 delete mainTLB;
129 }
130
131 const SMMUv3SlaveInterfaceParams *
132 params() const
133 {
134 return static_cast<const SMMUv3SlaveInterfaceParams *>(_params);
135 }
136
137 DrainState drain() override;
138
139 void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
140 void sendRange();
141};
142
143#endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */
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