1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
41#define __DEV_ARM_SMMU_V3_SLAVEIFC_HH__
42
43#include <list>
44
45#include "dev/arm/smmu_v3_caches.hh"
46#include "dev/arm/smmu_v3_defs.hh"
47#include "dev/arm/smmu_v3_events.hh"
48#include "dev/arm/smmu_v3_ports.hh"
49#include "dev/arm/smmu_v3_proc.hh"
50#include "mem/mem_object.hh"
51#include "params/SMMUv3SlaveInterface.hh"
52
53class SMMUTranslationProcess;
54class SMMUv3;
55class SMMUSlavePort;
56
57class SMMUv3SlaveInterface : public MemObject
58{
59 public:
60 SMMUv3 *smmu;
61 SMMUTLB* microTLB;
62 SMMUTLB* mainTLB;
63
64 const bool microTLBEnable;
65 const bool mainTLBEnable;
66
67 SMMUSemaphore slavePortSem;
68 SMMUSemaphore microTLBSem;
69 SMMUSemaphore mainTLBSem;
70
71 const Cycles microTLBLat;
72 const Cycles mainTLBLat;
73
74 SMMUSlavePort *slavePort;
75 SMMUATSSlavePort atsSlavePort;
76 SMMUATSMasterPort atsMasterPort;
77
78 // in bytes
79 const unsigned portWidth;
80
81 unsigned wrBufSlotsRemaining;
82 unsigned xlateSlotsRemaining;
83
84 const bool prefetchEnable;
85 const bool prefetchReserveLastWay;
86
87 std::list<SMMUTranslationProcess *> duplicateReqs;
88 SMMUSignal duplicateReqRemoved;
89
90 std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID];
91 std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
92 SMMUSignal dependentReqRemoved;
93
94 // Receiving translation requests from the master device
95 Tick recvAtomic(PacketPtr pkt);
96 bool recvTimingReq(PacketPtr pkt);
97 void schedTimingResp(PacketPtr pkt);
98
99 Tick atsSlaveRecvAtomic(PacketPtr pkt);
100 bool atsSlaveRecvTimingReq(PacketPtr pkt);
101 bool atsMasterRecvTimingResp(PacketPtr pkt);
102 void schedAtsTimingResp(PacketPtr pkt);
103
104 void scheduleDeviceRetry();
105 void sendDeviceRetry();
106 void atsSendDeviceRetry();
107
108 bool deviceNeedsRetry;
109 bool atsDeviceNeedsRetry;
110
111 SMMUDeviceRetryEvent sendDeviceRetryEvent;
112 EventWrapper<
113 SMMUv3SlaveInterface,
114 &SMMUv3SlaveInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent;
115
116 Port& getPort(const std::string &name, PortID id);
117
118 public:
119 SMMUv3SlaveInterface(const SMMUv3SlaveInterfaceParams *p);
120
121 ~SMMUv3SlaveInterface()
122 {
123 delete microTLB;
124 delete mainTLB;
125 }
126
127 void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
128 void sendRange();
129};
130
131#endif /* __DEV_ARM_SMMU_V3_SLAVEIFC_HH__ */