smmu_v3_defs.hh (14039:4991b2a345a1) smmu_v3_defs.hh (14065:f925f90bda01)
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 78 unchanged lines hidden (view full) ---

87 ST_CFG_FMT_LINEAR = 0x0000000000000000ULL,
88 ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL,
89 ST_L2_SPAN_MASK = 0x000000000000001fULL,
90 ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
91
92 VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
93 VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
94
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 78 unchanged lines hidden (view full) ---

87 ST_CFG_FMT_LINEAR = 0x0000000000000000ULL,
88 ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL,
89 ST_L2_SPAN_MASK = 0x000000000000001fULL,
90 ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
91
92 VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
93 VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
94
95 Q_CONS_PROD_MASK = 0x00000000000fffffULL,
96 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
97 Q_BASE_SIZE_MASK = 0x000000000000001fULL,
98
99 E_BASE_ENABLE_MASK = 0x8000000000000000ULL,
100 E_BASE_ADDR_MASK = 0x0000fffffffffffcULL,
101};
102
103union SMMURegs

--- 260 unchanged lines hidden --- 		95 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
96 Q_BASE_SIZE_MASK = 0x000000000000001fULL,
97
98 E_BASE_ENABLE_MASK = 0x8000000000000000ULL,
99 E_BASE_ADDR_MASK = 0x0000fffffffffffcULL,
100};
101
102union SMMURegs

--- 260 unchanged lines hidden ---