1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_DEFS_HH__
41#define __DEV_ARM_SMMU_V3_DEFS_HH__
42
43#include <stdint.h>
44
45#include "base/bitunion.hh"
46
47enum {
48 SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
49 SMMU_PAGE_ZERO_SZ = 0x10000,
50 SMMU_PAGE_ONE_SZ = 0x10000,
51 SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ
52};
53
54enum {
55 STE_CONFIG_ABORT = 0x0,
56 STE_CONFIG_BYPASS = 0x4,
57 STE_CONFIG_STAGE1_ONLY = 0x5,
58 STE_CONFIG_STAGE2_ONLY = 0x6,
59 STE_CONFIG_STAGE1_AND_2 = 0x7,
60};
61
62enum {
63 STAGE1_CFG_1L = 0x0,
64 STAGE1_CFG_2L_4K = 0x1,
65 STAGE1_CFG_2L_64K = 0x2,
66};
67
68enum {
69 ST_CFG_SPLIT_SHIFT = 6,
70 ST_CD_ADDR_SHIFT = 6,
71 CD_TTB_SHIFT = 4,
72 STE_S2TTB_SHIFT = 4,
73};
74
75enum {
76 TRANS_GRANULE_4K = 0x0,
77 TRANS_GRANULE_64K = 0x1,
78 TRANS_GRANULE_16K = 0x2,
79 TRANS_GRANULE_INVALID = 0x3,
80};
81
82enum {
83 ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
84 ST_CFG_SIZE_MASK = 0x000000000000003fULL,
85 ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL,
86 ST_CFG_FMT_MASK = 0x0000000000030000ULL,
87 ST_CFG_FMT_LINEAR = 0x0000000000000000ULL,
88 ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL,
89 ST_L2_SPAN_MASK = 0x000000000000001fULL,
90 ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
91
92 VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
93 VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
94
95 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
96 Q_BASE_SIZE_MASK = 0x000000000000001fULL,
97
98 E_BASE_ENABLE_MASK = 0x8000000000000000ULL,
99 E_BASE_ADDR_MASK = 0x0000fffffffffffcULL,
100};
101
102union SMMURegs
103{
104 uint8_t data[SMMU_REG_SIZE];
105
106 struct
107 {
108 uint32_t idr0; // 0x0000
109 uint32_t idr1; // 0x0004
110 uint32_t idr2; // 0x0008
111 uint32_t idr3; // 0x000c
112 uint32_t idr4; // 0x0010
113 uint32_t idr5; // 0x0014
114 uint32_t iidr; // 0x0018
115 uint32_t aidr; // 0x001c
116 uint32_t cr0; // 0x0020
117 uint32_t cr0ack; // 0x0024
118 uint32_t cr1; // 0x0028
119 uint32_t cr2; // 0x002c
120 uint32_t _pad1; // 0x0030
121 uint32_t _pad2; // 0x0034
122 uint32_t _pad3; // 0x0038
123 uint32_t _pad4; // 0x003c
124 uint32_t statusr; // 0x0040
125 uint32_t gbpa; // 0x0044
126 uint32_t agbpa; // 0x0048
127 uint32_t _pad5; // 0x004c
128 uint32_t irq_ctrl; // 0x0050
129 uint32_t irq_ctrlack; // 0x0054
130 uint32_t _pad6; // 0x0058
131 uint32_t _pad7; // 0x005c
132
133 uint32_t gerror; // 0x0060
134 uint32_t gerrorn; // 0x0064
135 uint64_t gerror_irq_cfg0; // 0x0068, 64 bit
136 uint32_t gerror_irq_cfg1; // 0x0070
137 uint32_t gerror_irq_cfg2; // 0x0074
138 uint32_t _pad_1; // 0x0078
139 uint32_t _pad_2; // 0x007c
140
141 uint64_t strtab_base; // 0x0080, 64 bit
142 uint32_t strtab_base_cfg; // 0x0088
143
144 uint64_t cmdq_base; // 0x0090, 64 bit
145 uint32_t cmdq_prod; // 0x0098
146 uint32_t cmdq_cons; // 0x009c
147 uint64_t eventq_base; // 0x00a0, 64 bit
148 uint32_t _pad8; // 0x00a8
149 uint32_t _pad9; // 0x00ac
150 uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit
151 uint32_t eventq_irq_cfg1; // 0x00b8
152 uint32_t eventq_irq_cfg2; // 0x00bc
153 uint64_t priq_base; // 0x00c0, 64 bit
154 uint32_t _pad10; // 0x00c8
155 uint32_t _pad11; // 0x00cc
156
157 uint64_t priq_irq_cfg0; // 0x00d0
158 uint32_t priq_irq_cfg1; // 0x00d8
159 uint32_t priq_irq_cfg2; // 0x00dc
160
161 uint32_t _pad12[8]; // 0x00e0 - 0x0100
162 uint32_t gatos_ctrl; // 0x0100
163 uint32_t _pad13; // 0x0104
164 uint64_t gatos_sid; // 0x0108
165 uint64_t gatos_addr; // 0x0110
166 uint64_t gatos_par; // 0x0118
167 uint32_t _pad14[24]; // 0x0120
168 uint32_t vatos_sel; // 0x0180
169
170 uint32_t _pad15[8095]; // 0x184 - 0x7ffc
171
172 uint8_t _secure_regs[SMMU_SECURE_SZ]; // 0x8000 - 0x8180
173
174 uint32_t _pad16[8095]; // 0x8184 - 0x10000
175
176 // Page 1
177 uint32_t _pad17[42]; // 0x10000
178 uint32_t eventq_prod; // 0x100A8
179 uint32_t eventq_cons; // 0x100AC
180
181 uint32_t _pad18[6]; // 0x100B0
182 uint32_t priq_prod; // 0x100C8
183 uint32_t priq_cons; // 0x100CC
184 };
185};
186
187struct StreamTableEntry
188{
189 BitUnion64(DWORD0)
190 Bitfield<0> valid;
191 Bitfield<3, 1> config;
192 Bitfield<5, 4> s1fmt;
193 Bitfield<51, 6> s1ctxptr;
194 Bitfield<63, 59> s1cdmax;
195 EndBitUnion(DWORD0)
196 DWORD0 dw0;
197
198 BitUnion64(DWORD1)
199 Bitfield<1, 0> s1dss;
200 Bitfield<3, 2> s1cir;
201 Bitfield<5, 4> s1cor;
202 Bitfield<7, 6> s1csh;
203 Bitfield<8> s2hwu59;
204 Bitfield<9> s2hwu60;
205 Bitfield<10> s2hwu61;
206 Bitfield<11> s2hwu62;
207 Bitfield<12> dre;
208 Bitfield<16, 13> cont;
209 Bitfield<17> dcp;
210 Bitfield<18> ppar;
211 Bitfield<19> mev;
212 Bitfield<27> s1stalld;
213 Bitfield<29, 28> eats;
214 Bitfield<31, 30> strw;
215 Bitfield<35, 32> memattr;
216 Bitfield<36> mtcfg;
217 Bitfield<40, 37> alloccfg;
218 Bitfield<45, 44> shcfg;
219 Bitfield<47, 46> nscfg;
220 Bitfield<49, 48> privcfg;
221 Bitfield<51, 50> instcfg;
222 EndBitUnion(DWORD1)
223 DWORD1 dw1;
224
225 BitUnion64(DWORD2)
226 Bitfield<15, 0> s2vmid;
227 Bitfield<37, 32> s2t0sz;
228 Bitfield<39, 38> s2sl0;
229 Bitfield<41, 40> s2ir0;
230 Bitfield<43, 42> s2or0;
231 Bitfield<45, 44> s2sh0;
232 Bitfield<47, 46> s2tg;
233 Bitfield<50, 48> s2ps;
234 Bitfield<51> s2aa64;
235 Bitfield<52> s2endi;
236 Bitfield<53> s2affd;
237 Bitfield<54> s2ptw;
238 Bitfield<55> s2hd;
239 Bitfield<56> s2ha;
240 Bitfield<57> s2s;
241 Bitfield<58> s2r;
242 EndBitUnion(DWORD2)
243 DWORD2 dw2;
244
245 BitUnion64(DWORD3)
246 Bitfield<51, 4> s2ttb;
247 EndBitUnion(DWORD3)
248 DWORD3 dw3;
249
250 uint64_t _pad[4];
251};
252
253struct ContextDescriptor
254{
255 BitUnion64(DWORD0)
256 Bitfield<5, 0> t0sz;
257 Bitfield<7, 6> tg0;
258 Bitfield<9, 8> ir0;
259 Bitfield<11, 10> or0;
260 Bitfield<13, 12> sh0;
261 Bitfield<14> epd0;
262 Bitfield<15> endi;
263 Bitfield<21, 16> t1sz;
264 Bitfield<23, 22> tg1;
265 Bitfield<25, 24> ir1;
266 Bitfield<27, 26> or1;
267 Bitfield<29, 28> sh1;
268 Bitfield<30> epd1;
269 Bitfield<31> valid;
270 Bitfield<34, 32> ips;
271 Bitfield<35> affd;
272 Bitfield<36> wxn;
273 Bitfield<37> uwxn;
274 Bitfield<39, 38> tbi;
275 Bitfield<40> pan;
276 Bitfield<41> aa64;
277 Bitfield<42> hd;
278 Bitfield<43> ha;
279 Bitfield<44> s;
280 Bitfield<45> r;
281 Bitfield<46> a;
282 Bitfield<47> aset;
283 Bitfield<63, 48> asid;
284 EndBitUnion(DWORD0)
285 DWORD0 dw0;
286
287 BitUnion64(DWORD1)
288 Bitfield<0> nscfg0;
289 Bitfield<1> had0;
290 Bitfield<51, 4> ttb0;
291 Bitfield<60> hwu0g59;
292 Bitfield<61> hwu0g60;
293 Bitfield<62> hwu0g61;
294 Bitfield<63> hwu0g62;
295 EndBitUnion(DWORD1)
296 DWORD1 dw1;
297
298 BitUnion64(DWORD2)
299 Bitfield<0> nscfg1;
300 Bitfield<1> had1;
301 Bitfield<51, 4> ttb1;
302 Bitfield<60> hwu1g59;
303 Bitfield<61> hwu1g60;
304 Bitfield<62> hwu1g61;
305 Bitfield<63> hwu1g62;
306 EndBitUnion(DWORD2)
307 DWORD2 dw2;
308
309 uint64_t mair;
310 uint64_t amair;
311 uint64_t _pad[3];
312};
313
314enum {
315 CR0_SMMUEN_MASK = 0x1,
316 CR0_PRIQEN_MASK = 0x2,
317 CR0_EVENTQEN_MASK = 0x4,
318 CR0_CMDQEN_MASK = 0x8,
319 CR0_ATSCHK_MASK = 0x10,
320 CR0_VMW_MASK = 0x1C0,
321};
322
323enum SMMUCommandType {
| 1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_DEFS_HH__
41#define __DEV_ARM_SMMU_V3_DEFS_HH__
42
43#include <stdint.h>
44
45#include "base/bitunion.hh"
46
47enum {
48 SMMU_SECURE_SZ = 0x184, // Secure regs are within page0
49 SMMU_PAGE_ZERO_SZ = 0x10000,
50 SMMU_PAGE_ONE_SZ = 0x10000,
51 SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ
52};
53
54enum {
55 STE_CONFIG_ABORT = 0x0,
56 STE_CONFIG_BYPASS = 0x4,
57 STE_CONFIG_STAGE1_ONLY = 0x5,
58 STE_CONFIG_STAGE2_ONLY = 0x6,
59 STE_CONFIG_STAGE1_AND_2 = 0x7,
60};
61
62enum {
63 STAGE1_CFG_1L = 0x0,
64 STAGE1_CFG_2L_4K = 0x1,
65 STAGE1_CFG_2L_64K = 0x2,
66};
67
68enum {
69 ST_CFG_SPLIT_SHIFT = 6,
70 ST_CD_ADDR_SHIFT = 6,
71 CD_TTB_SHIFT = 4,
72 STE_S2TTB_SHIFT = 4,
73};
74
75enum {
76 TRANS_GRANULE_4K = 0x0,
77 TRANS_GRANULE_64K = 0x1,
78 TRANS_GRANULE_16K = 0x2,
79 TRANS_GRANULE_INVALID = 0x3,
80};
81
82enum {
83 ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
84 ST_CFG_SIZE_MASK = 0x000000000000003fULL,
85 ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL,
86 ST_CFG_FMT_MASK = 0x0000000000030000ULL,
87 ST_CFG_FMT_LINEAR = 0x0000000000000000ULL,
88 ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL,
89 ST_L2_SPAN_MASK = 0x000000000000001fULL,
90 ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
91
92 VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
93 VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
94
95 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
96 Q_BASE_SIZE_MASK = 0x000000000000001fULL,
97
98 E_BASE_ENABLE_MASK = 0x8000000000000000ULL,
99 E_BASE_ADDR_MASK = 0x0000fffffffffffcULL,
100};
101
102union SMMURegs
103{
104 uint8_t data[SMMU_REG_SIZE];
105
106 struct
107 {
108 uint32_t idr0; // 0x0000
109 uint32_t idr1; // 0x0004
110 uint32_t idr2; // 0x0008
111 uint32_t idr3; // 0x000c
112 uint32_t idr4; // 0x0010
113 uint32_t idr5; // 0x0014
114 uint32_t iidr; // 0x0018
115 uint32_t aidr; // 0x001c
116 uint32_t cr0; // 0x0020
117 uint32_t cr0ack; // 0x0024
118 uint32_t cr1; // 0x0028
119 uint32_t cr2; // 0x002c
120 uint32_t _pad1; // 0x0030
121 uint32_t _pad2; // 0x0034
122 uint32_t _pad3; // 0x0038
123 uint32_t _pad4; // 0x003c
124 uint32_t statusr; // 0x0040
125 uint32_t gbpa; // 0x0044
126 uint32_t agbpa; // 0x0048
127 uint32_t _pad5; // 0x004c
128 uint32_t irq_ctrl; // 0x0050
129 uint32_t irq_ctrlack; // 0x0054
130 uint32_t _pad6; // 0x0058
131 uint32_t _pad7; // 0x005c
132
133 uint32_t gerror; // 0x0060
134 uint32_t gerrorn; // 0x0064
135 uint64_t gerror_irq_cfg0; // 0x0068, 64 bit
136 uint32_t gerror_irq_cfg1; // 0x0070
137 uint32_t gerror_irq_cfg2; // 0x0074
138 uint32_t _pad_1; // 0x0078
139 uint32_t _pad_2; // 0x007c
140
141 uint64_t strtab_base; // 0x0080, 64 bit
142 uint32_t strtab_base_cfg; // 0x0088
143
144 uint64_t cmdq_base; // 0x0090, 64 bit
145 uint32_t cmdq_prod; // 0x0098
146 uint32_t cmdq_cons; // 0x009c
147 uint64_t eventq_base; // 0x00a0, 64 bit
148 uint32_t _pad8; // 0x00a8
149 uint32_t _pad9; // 0x00ac
150 uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit
151 uint32_t eventq_irq_cfg1; // 0x00b8
152 uint32_t eventq_irq_cfg2; // 0x00bc
153 uint64_t priq_base; // 0x00c0, 64 bit
154 uint32_t _pad10; // 0x00c8
155 uint32_t _pad11; // 0x00cc
156
157 uint64_t priq_irq_cfg0; // 0x00d0
158 uint32_t priq_irq_cfg1; // 0x00d8
159 uint32_t priq_irq_cfg2; // 0x00dc
160
161 uint32_t _pad12[8]; // 0x00e0 - 0x0100
162 uint32_t gatos_ctrl; // 0x0100
163 uint32_t _pad13; // 0x0104
164 uint64_t gatos_sid; // 0x0108
165 uint64_t gatos_addr; // 0x0110
166 uint64_t gatos_par; // 0x0118
167 uint32_t _pad14[24]; // 0x0120
168 uint32_t vatos_sel; // 0x0180
169
170 uint32_t _pad15[8095]; // 0x184 - 0x7ffc
171
172 uint8_t _secure_regs[SMMU_SECURE_SZ]; // 0x8000 - 0x8180
173
174 uint32_t _pad16[8095]; // 0x8184 - 0x10000
175
176 // Page 1
177 uint32_t _pad17[42]; // 0x10000
178 uint32_t eventq_prod; // 0x100A8
179 uint32_t eventq_cons; // 0x100AC
180
181 uint32_t _pad18[6]; // 0x100B0
182 uint32_t priq_prod; // 0x100C8
183 uint32_t priq_cons; // 0x100CC
184 };
185};
186
187struct StreamTableEntry
188{
189 BitUnion64(DWORD0)
190 Bitfield<0> valid;
191 Bitfield<3, 1> config;
192 Bitfield<5, 4> s1fmt;
193 Bitfield<51, 6> s1ctxptr;
194 Bitfield<63, 59> s1cdmax;
195 EndBitUnion(DWORD0)
196 DWORD0 dw0;
197
198 BitUnion64(DWORD1)
199 Bitfield<1, 0> s1dss;
200 Bitfield<3, 2> s1cir;
201 Bitfield<5, 4> s1cor;
202 Bitfield<7, 6> s1csh;
203 Bitfield<8> s2hwu59;
204 Bitfield<9> s2hwu60;
205 Bitfield<10> s2hwu61;
206 Bitfield<11> s2hwu62;
207 Bitfield<12> dre;
208 Bitfield<16, 13> cont;
209 Bitfield<17> dcp;
210 Bitfield<18> ppar;
211 Bitfield<19> mev;
212 Bitfield<27> s1stalld;
213 Bitfield<29, 28> eats;
214 Bitfield<31, 30> strw;
215 Bitfield<35, 32> memattr;
216 Bitfield<36> mtcfg;
217 Bitfield<40, 37> alloccfg;
218 Bitfield<45, 44> shcfg;
219 Bitfield<47, 46> nscfg;
220 Bitfield<49, 48> privcfg;
221 Bitfield<51, 50> instcfg;
222 EndBitUnion(DWORD1)
223 DWORD1 dw1;
224
225 BitUnion64(DWORD2)
226 Bitfield<15, 0> s2vmid;
227 Bitfield<37, 32> s2t0sz;
228 Bitfield<39, 38> s2sl0;
229 Bitfield<41, 40> s2ir0;
230 Bitfield<43, 42> s2or0;
231 Bitfield<45, 44> s2sh0;
232 Bitfield<47, 46> s2tg;
233 Bitfield<50, 48> s2ps;
234 Bitfield<51> s2aa64;
235 Bitfield<52> s2endi;
236 Bitfield<53> s2affd;
237 Bitfield<54> s2ptw;
238 Bitfield<55> s2hd;
239 Bitfield<56> s2ha;
240 Bitfield<57> s2s;
241 Bitfield<58> s2r;
242 EndBitUnion(DWORD2)
243 DWORD2 dw2;
244
245 BitUnion64(DWORD3)
246 Bitfield<51, 4> s2ttb;
247 EndBitUnion(DWORD3)
248 DWORD3 dw3;
249
250 uint64_t _pad[4];
251};
252
253struct ContextDescriptor
254{
255 BitUnion64(DWORD0)
256 Bitfield<5, 0> t0sz;
257 Bitfield<7, 6> tg0;
258 Bitfield<9, 8> ir0;
259 Bitfield<11, 10> or0;
260 Bitfield<13, 12> sh0;
261 Bitfield<14> epd0;
262 Bitfield<15> endi;
263 Bitfield<21, 16> t1sz;
264 Bitfield<23, 22> tg1;
265 Bitfield<25, 24> ir1;
266 Bitfield<27, 26> or1;
267 Bitfield<29, 28> sh1;
268 Bitfield<30> epd1;
269 Bitfield<31> valid;
270 Bitfield<34, 32> ips;
271 Bitfield<35> affd;
272 Bitfield<36> wxn;
273 Bitfield<37> uwxn;
274 Bitfield<39, 38> tbi;
275 Bitfield<40> pan;
276 Bitfield<41> aa64;
277 Bitfield<42> hd;
278 Bitfield<43> ha;
279 Bitfield<44> s;
280 Bitfield<45> r;
281 Bitfield<46> a;
282 Bitfield<47> aset;
283 Bitfield<63, 48> asid;
284 EndBitUnion(DWORD0)
285 DWORD0 dw0;
286
287 BitUnion64(DWORD1)
288 Bitfield<0> nscfg0;
289 Bitfield<1> had0;
290 Bitfield<51, 4> ttb0;
291 Bitfield<60> hwu0g59;
292 Bitfield<61> hwu0g60;
293 Bitfield<62> hwu0g61;
294 Bitfield<63> hwu0g62;
295 EndBitUnion(DWORD1)
296 DWORD1 dw1;
297
298 BitUnion64(DWORD2)
299 Bitfield<0> nscfg1;
300 Bitfield<1> had1;
301 Bitfield<51, 4> ttb1;
302 Bitfield<60> hwu1g59;
303 Bitfield<61> hwu1g60;
304 Bitfield<62> hwu1g61;
305 Bitfield<63> hwu1g62;
306 EndBitUnion(DWORD2)
307 DWORD2 dw2;
308
309 uint64_t mair;
310 uint64_t amair;
311 uint64_t _pad[3];
312};
313
314enum {
315 CR0_SMMUEN_MASK = 0x1,
316 CR0_PRIQEN_MASK = 0x2,
317 CR0_EVENTQEN_MASK = 0x4,
318 CR0_CMDQEN_MASK = 0x8,
319 CR0_ATSCHK_MASK = 0x10,
320 CR0_VMW_MASK = 0x1C0,
321};
322
323enum SMMUCommandType {
|
324 CMD_PRF_CONFIG = 0x1000,
325 CMD_PRF_ADDR = 0x1001,
326 CMD_INV_STE = 0x1100,
327 CMD_INV_CD = 0x1101,
328 CMD_INV_CD_ALL = 0x1102,
329 CMD_INV_ALL = 0x1104,
330 CMD_TLBI_ALL = 0x1110,
331 CMD_TLBI_ASID = 0x1111,
332 CMD_TLBI_VAAL = 0x1112,
333 CMD_TLBI_VAA = 0x1113,
334 CMD_TLBI_VAL = 0x1114,
335 CMD_TLBI_VA = 0x1115,
336 CMD_TLBI_VM_IPAL = 0x1120,
337 CMD_TLBI_VM_IPA = 0x1121,
338 CMD_TLBI_VM_S12 = 0x1122,
339 CMD_RESUME_S = 0x1200,
| 324 CMD_PRF_CONFIG = 0x01,
325 CMD_PRF_ADDR = 0x02,
326 CMD_CFGI_STE = 0x03,
327 CMD_CFGI_STE_RANGE = 0x04,
328 CMD_CFGI_CD = 0x05,
329 CMD_CFGI_CD_ALL = 0x06,
330 CMD_TLBI_NH_ALL = 0x10,
331 CMD_TLBI_NH_ASID = 0x11,
332 CMD_TLBI_NH_VAA = 0x13,
333 CMD_TLBI_NH_VA = 0x12,
334 CMD_TLBI_EL3_ALL = 0x18,
335 CMD_TLBI_EL3_VA = 0x1A,
336 CMD_TLBI_EL2_ALL = 0x20,
337 CMD_TLBI_EL2_ASID = 0x21,
338 CMD_TLBI_EL2_VA = 0x22,
339 CMD_TLBI_EL2_VAA = 0x23,
340 CMD_TLBI_S2_IPA = 0x2a,
341 CMD_TLBI_S12_VMALL = 0x28,
342 CMD_TLBI_NSNH_ALL = 0x30,
343 CMD_ATC_INV = 0x40,
344 CMD_PRI_RESP = 0x41,
345 CMD_RESUME = 0x44,
346 CMD_STALL_TERM = 0x45,
347 CMD_SYNC = 0x46,
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