1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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316 CR0_PRIQEN_MASK = 0x2,
317 CR0_EVENTQEN_MASK = 0x4,
318 CR0_CMDQEN_MASK = 0x8,
319 CR0_ATSCHK_MASK = 0x10,
320 CR0_VMW_MASK = 0x1C0,
321};
322
323enum SMMUCommandType {
324 CMD_PRF_CONFIG = 0x1000,
325 CMD_PRF_ADDR = 0x1001,
326 CMD_INV_STE = 0x1100,
327 CMD_INV_CD = 0x1101,
328 CMD_INV_CD_ALL = 0x1102,
329 CMD_INV_ALL = 0x1104,
330 CMD_TLBI_ALL = 0x1110,
331 CMD_TLBI_ASID = 0x1111,
332 CMD_TLBI_VAAL = 0x1112,
333 CMD_TLBI_VAA = 0x1113,
334 CMD_TLBI_VAL = 0x1114,
335 CMD_TLBI_VA = 0x1115,
336 CMD_TLBI_VM_IPAL = 0x1120,
337 CMD_TLBI_VM_IPA = 0x1121,
338 CMD_TLBI_VM_S12 = 0x1122,
339 CMD_RESUME_S = 0x1200,
340};
341
342struct SMMUCommand
343{
344 uint32_t type;
345 uint32_t data[3];
346};
347
348enum SMMUEventTypes {
349 EVT_FAULT = 0x0001,
350};
351
352enum SMMUEventFlags {
353 EVF_WRITE = 0x0001,

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