1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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316 CR0_PRIQEN_MASK = 0x2,
317 CR0_EVENTQEN_MASK = 0x4,
318 CR0_CMDQEN_MASK = 0x8,
319 CR0_ATSCHK_MASK = 0x10,
320 CR0_VMW_MASK = 0x1C0,
321};
322
323enum SMMUCommandType {
324 CMD_PRF_CONFIG = 0x01,
325 CMD_PRF_ADDR = 0x02,
326 CMD_CFGI_STE = 0x03,
327 CMD_CFGI_STE_RANGE = 0x04,
328 CMD_CFGI_CD = 0x05,
329 CMD_CFGI_CD_ALL = 0x06,
330 CMD_TLBI_NH_ALL = 0x10,
331 CMD_TLBI_NH_ASID = 0x11,
332 CMD_TLBI_NH_VAA = 0x13,
333 CMD_TLBI_NH_VA = 0x12,
334 CMD_TLBI_EL3_ALL = 0x18,
335 CMD_TLBI_EL3_VA = 0x1A,
336 CMD_TLBI_EL2_ALL = 0x20,
337 CMD_TLBI_EL2_ASID = 0x21,
338 CMD_TLBI_EL2_VA = 0x22,
339 CMD_TLBI_EL2_VAA = 0x23,
340 CMD_TLBI_S2_IPA = 0x2a,
341 CMD_TLBI_S12_VMALL = 0x28,
342 CMD_TLBI_NSNH_ALL = 0x30,
343 CMD_ATC_INV = 0x40,
344 CMD_PRI_RESP = 0x41,
345 CMD_RESUME = 0x44,
346 CMD_STALL_TERM = 0x45,
347 CMD_SYNC = 0x46,
348};
349
350struct SMMUCommand
351{
352 BitUnion64(DWORD0)
353 Bitfield<7, 0> type;
354 Bitfield<10> ssec;
355 Bitfield<11> ssv;
356 Bitfield<31, 12> ssid;
357 Bitfield<47, 32> vmid;
358 Bitfield<63, 48> asid;
359 Bitfield<63, 32> sid;
360 EndBitUnion(DWORD0)
361 DWORD0 dw0;
362
363 BitUnion64(DWORD1)
364 Bitfield<0> leaf;
365 Bitfield<4, 0> size;
366 Bitfield<4, 0> range;
367 Bitfield<63, 12> address;
368 EndBitUnion(DWORD1)
369 DWORD1 dw1;
370
371 uint64_t addr() const
372 {
373 uint64_t address = (uint64_t)(dw1.address) << 12;
374 return address;
375 }
376};
377
378enum SMMUEventTypes {
379 EVT_FAULT = 0x0001,
380};
381
382enum SMMUEventFlags {
383 EVF_WRITE = 0x0001,

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