smmu_v3.cc (14221:2954f631ee64) smmu_v3.cc (14252:1659a606447f)
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "base/types.hh"
50#include "debug/Checkpoint.hh"
51#include "debug/SMMUv3.hh"
52#include "dev/arm/smmu_v3_transl.hh"
53#include "mem/packet_access.hh"
54#include "sim/system.hh"
55
56SMMUv3::SMMUv3(SMMUv3Params *params) :
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "base/types.hh"
50#include "debug/Checkpoint.hh"
51#include "debug/SMMUv3.hh"
52#include "dev/arm/smmu_v3_transl.hh"
53#include "mem/packet_access.hh"
54#include "sim/system.hh"
55
56SMMUv3::SMMUv3(SMMUv3Params *params) :
57 MemObject(params),
57 ClockedObject(params),
58 system(*params->system),
59 masterId(params->system->getMasterId(this)),
60 masterPort(name() + ".master", *this),
61 masterTableWalkPort(name() + ".master_walker", *this),
62 controlPort(name() + ".control", *this, params->reg_map),
63 tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy),
64 configCache(params->cfg_entries, params->cfg_assoc, params->cfg_policy),
65 ipaCache(params->ipa_entries, params->ipa_assoc, params->ipa_policy),

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734
735 if (controlPort.isConnected())
736 controlPort.sendRangeChange();
737}
738
739void
740SMMUv3::regStats()
741{
58 system(*params->system),
59 masterId(params->system->getMasterId(this)),
60 masterPort(name() + ".master", *this),
61 masterTableWalkPort(name() + ".master_walker", *this),
62 controlPort(name() + ".control", *this, params->reg_map),
63 tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy),
64 configCache(params->cfg_entries, params->cfg_assoc, params->cfg_policy),
65 ipaCache(params->ipa_entries, params->ipa_assoc, params->ipa_policy),

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734
735 if (controlPort.isConnected())
736 controlPort.sendRangeChange();
737}
738
739void
740SMMUv3::regStats()
741{
742 MemObject::regStats();
742 ClockedObject::regStats();
743
744 using namespace Stats;
745
746 for (size_t i = 0; i < slaveInterfaces.size(); i++) {
747 slaveInterfaces[i]->microTLB->regStats(
748 csprintf("%s.utlb%d", name(), i));
749 slaveInterfaces[i]->mainTLB->regStats(
750 csprintf("%s.maintlb%d", name(), i));

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819{
820 if (name == "master") {
821 return masterPort;
822 } else if (name == "master_walker") {
823 return masterTableWalkPort;
824 } else if (name == "control") {
825 return controlPort;
826 } else {
743
744 using namespace Stats;
745
746 for (size_t i = 0; i < slaveInterfaces.size(); i++) {
747 slaveInterfaces[i]->microTLB->regStats(
748 csprintf("%s.utlb%d", name(), i));
749 slaveInterfaces[i]->mainTLB->regStats(
750 csprintf("%s.maintlb%d", name(), i));

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819{
820 if (name == "master") {
821 return masterPort;
822 } else if (name == "master_walker") {
823 return masterTableWalkPort;
824 } else if (name == "control") {
825 return controlPort;
826 } else {
827 return MemObject::getPort(name, id);
827 return ClockedObject::getPort(name, id);
828 }
829}
830
831SMMUv3*
832SMMUv3Params::create()
833{
834 return new SMMUv3(this);
835}
828 }
829}
830
831SMMUv3*
832SMMUv3Params::create()
833{
834 return new SMMUv3(this);
835}