1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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378 } else {
379 panic("Not in timing or atomic mode!");
380 }
381}
382
383void
384SMMUv3::processCommand(const SMMUCommand &cmd)
385{
386 switch (cmd.type) {
387 case CMD_PRF_CONFIG:
388 DPRINTF(SMMUv3, "CMD_PREFETCH_CONFIG - ignored\n");
389 break;
390
391 case CMD_PRF_ADDR:
392 DPRINTF(SMMUv3, "CMD_PREFETCH_ADDR - ignored\n");
393 break;
394
395 case CMD_INV_STE:
396 DPRINTF(SMMUv3, "CMD_INV_STE sid=%#x\n", cmd.data[0]);
397 configCache.invalidateSID(cmd.data[0]);
398 break;
399
400 case CMD_INV_CD:
401 DPRINTF(SMMUv3, "CMD_INV_CD sid=%#x ssid=%#x\n",
402 cmd.data[0], cmd.data[1]);
403 configCache.invalidateSSID(cmd.data[0], cmd.data[1]);
404 break;
405
406 case CMD_INV_CD_ALL:
407 DPRINTF(SMMUv3, "CMD_INV_CD_ALL sid=%#x\n", cmd.data[0]);
408 configCache.invalidateSID(cmd.data[0]);
409 break;
410
411 case CMD_INV_ALL:
412 DPRINTF(SMMUv3, "CMD_INV_ALL\n");
413 configCache.invalidateAll();
414 break;
415
416 case CMD_TLBI_ALL:
417 DPRINTF(SMMUv3, "CMD_TLBI_ALL\n");
418 for (auto slave_interface : slaveInterfaces) {
419 slave_interface->microTLB->invalidateAll();
420 slave_interface->mainTLB->invalidateAll();
421 }
422 tlb.invalidateAll();
423 ipaCache.invalidateAll();
424 walkCache.invalidateAll();
425 break;
426
427 case CMD_TLBI_ASID:
428 DPRINTF(SMMUv3, "CMD_TLBI_ASID asid=%#x vmid=%#x\n",
429 cmd.data[0], cmd.data[1]);
430 for (auto slave_interface : slaveInterfaces) {
431 slave_interface->microTLB->invalidateASID(
432 cmd.data[0], cmd.data[1]);
433 slave_interface->mainTLB->invalidateASID(
434 cmd.data[0], cmd.data[1]);
435 }
436 tlb.invalidateASID(cmd.data[0], cmd.data[1]);
437 walkCache.invalidateASID(cmd.data[0], cmd.data[1]);
438 break;
439
440 case CMD_TLBI_VAAL:
441 DPRINTF(SMMUv3, "CMD_TLBI_VAAL va=%#08x vmid=%#x\n",
442 cmd.data[0], cmd.data[1]);
443 for (auto slave_interface : slaveInterfaces) {
444 slave_interface->microTLB->invalidateVAA(
445 cmd.data[0], cmd.data[1]);
446 slave_interface->mainTLB->invalidateVAA(
447 cmd.data[0], cmd.data[1]);
448 }
449 tlb.invalidateVAA(cmd.data[0], cmd.data[1]);
450 break;
451
452 case CMD_TLBI_VAA:
453 DPRINTF(SMMUv3, "CMD_TLBI_VAA va=%#08x vmid=%#x\n",
454 cmd.data[0], cmd.data[1]);
455 for (auto slave_interface : slaveInterfaces) {
456 slave_interface->microTLB->invalidateVAA(
457 cmd.data[0], cmd.data[1]);
458 slave_interface->mainTLB->invalidateVAA(
459 cmd.data[0], cmd.data[1]);
460 }
461 tlb.invalidateVAA(cmd.data[0], cmd.data[1]);
462 walkCache.invalidateVAA(cmd.data[0], cmd.data[1]);
463 break;
464
465 case CMD_TLBI_VAL:
466 DPRINTF(SMMUv3, "CMD_TLBI_VAL va=%#08x asid=%#x vmid=%#x\n",
467 cmd.data[0], cmd.data[1], cmd.data[2]);
468 for (auto slave_interface : slaveInterfaces) {
469 slave_interface->microTLB->invalidateVA(
470 cmd.data[0], cmd.data[1], cmd.data[2]);
471 slave_interface->mainTLB->invalidateVA(
472 cmd.data[0], cmd.data[1], cmd.data[2]);
473 }
474 tlb.invalidateVA(cmd.data[0], cmd.data[1], cmd.data[2]);
475 break;
476
477 case CMD_TLBI_VA:
478 DPRINTF(SMMUv3, "CMD_TLBI_VA va=%#08x asid=%#x vmid=%#x\n",
479 cmd.data[0], cmd.data[1], cmd.data[2]);
480 for (auto slave_interface : slaveInterfaces) {
481 slave_interface->microTLB->invalidateVA(
482 cmd.data[0], cmd.data[1], cmd.data[2]);
483 slave_interface->mainTLB->invalidateVA(
484 cmd.data[0], cmd.data[1], cmd.data[2]);
485 }
486 tlb.invalidateVA(cmd.data[0], cmd.data[1], cmd.data[2]);
487 walkCache.invalidateVA(cmd.data[0], cmd.data[1], cmd.data[2]);
488 break;
489
490 case CMD_TLBI_VM_IPAL:
491 DPRINTF(SMMUv3, "CMD_TLBI_VM_IPAL ipa=%#08x vmid=%#x\n",
492 cmd.data[0], cmd.data[1]);
493 // This does not invalidate TLBs containing
494 // combined Stage1 + Stage2 translations, as per the spec.
495 ipaCache.invalidateIPA(cmd.data[0], cmd.data[1]);
496 walkCache.invalidateVMID(cmd.data[1]);
497 break;
498
499 case CMD_TLBI_VM_IPA:
500 DPRINTF(SMMUv3, "CMD_TLBI_VM_IPA ipa=%#08x vmid=%#x\n",
501 cmd.data[0], cmd.data[1]);
502 // This does not invalidate TLBs containing
503 // combined Stage1 + Stage2 translations, as per the spec.
504 ipaCache.invalidateIPA(cmd.data[0], cmd.data[1]);
505 walkCache.invalidateVMID(cmd.data[1]);
506 break;
507
508 case CMD_TLBI_VM_S12:
509 DPRINTF(SMMUv3, "CMD_TLBI_VM_S12 vmid=%#x\n", cmd.data[0]);
510 for (auto slave_interface : slaveInterfaces) {
511 slave_interface->microTLB->invalidateVMID(cmd.data[0]);
512 slave_interface->mainTLB->invalidateVMID(cmd.data[0]);
513 }
514 tlb.invalidateVMID(cmd.data[0]);
515 ipaCache.invalidateVMID(cmd.data[0]);
516 walkCache.invalidateVMID(cmd.data[0]);
517 break;
518
519 case CMD_RESUME_S:
520 DPRINTF(SMMUv3, "CMD_RESUME_S\n");
521 panic("resume unimplemented");
522 break;
523
524 default:
525 warn("Unimplemented command %#x\n", cmd.type);
526 break;
527 }
528}
529
530const PageTableOps*
531SMMUv3::getPageTableOps(uint8_t trans_granule)
532{
533 static V8PageTableOps4k ptOps4k;

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