rv_ctrl.hh (9235:5aa4896ed55a) | rv_ctrl.hh (9958:48eb085bc9ab) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited | 2 * Copyright (c) 2010,2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 64 unchanged lines hidden (view full) --- 75 Clcd = 0x50, 76 ClcdSer = 0x54, 77 Bootcs = 0x58, 78 Clock24 = 0x5C, 79 Misc = 0x60, 80 IoSel = 0x70, 81 ProcId0 = 0x84, 82 ProcId1 = 0x88, | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 64 unchanged lines hidden (view full) --- 75 Clcd = 0x50, 76 ClcdSer = 0x54, 77 Bootcs = 0x58, 78 Clock24 = 0x5C, 79 Misc = 0x60, 80 IoSel = 0x70, 81 ProcId0 = 0x84, 82 ProcId1 = 0x88, |
83 CfgCtrl = 0xA0, 84 CfgData = 0xA4, | 83 CfgData = 0xA0, 84 CfgCtrl = 0xA4, |
85 CfgStat = 0xA8, 86 TestOsc0 = 0xC0, 87 TestOsc1 = 0xC4, 88 TestOsc2 = 0xC8, 89 TestOsc3 = 0xCC, 90 TestOsc4 = 0xD0 91 }; 92 --- 7 unchanged lines hidden (view full) --- 100 101 /** This register is used for smp booting. 102 * The primary cpu writes the secondary start address here before 103 * sends it a soft interrupt. The secondary cpu reads this register and if 104 * it's non-zero it jumps to the address 105 */ 106 uint32_t flags; 107 | 85 CfgStat = 0xA8, 86 TestOsc0 = 0xC0, 87 TestOsc1 = 0xC4, 88 TestOsc2 = 0xC8, 89 TestOsc3 = 0xCC, 90 TestOsc4 = 0xD0 91 }; 92 --- 7 unchanged lines hidden (view full) --- 100 101 /** This register is used for smp booting. 102 * The primary cpu writes the secondary start address here before 103 * sends it a soft interrupt. The secondary cpu reads this register and if 104 * it's non-zero it jumps to the address 105 */ 106 uint32_t flags; 107 |
108 /** This register contains the result from a system control reg access 109 */ 110 uint32_t scData; 111 |
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108 public: 109 typedef RealViewCtrlParams Params; 110 const Params * 111 params() const 112 { 113 return dynamic_cast<const Params *>(_params); 114 } 115 /** --- 26 unchanged lines hidden --- | 112 public: 113 typedef RealViewCtrlParams Params; 114 const Params * 115 params() const 116 { 117 return dynamic_cast<const Params *>(_params); 118 } 119 /** --- 26 unchanged lines hidden --- |