rv_ctrl.cc (9808:13ffc0066b76) rv_ctrl.cc (9958:48eb085bc9ab)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/trace.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/trace.hh"
41#include "debug/RVCTRL.hh"
41#include "dev/arm/rv_ctrl.hh"
42#include "mem/packet.hh"
43#include "mem/packet_access.hh"
44
45RealViewCtrl::RealViewCtrl(Params *p)
42#include "dev/arm/rv_ctrl.hh"
43#include "mem/packet.hh"
44#include "mem/packet_access.hh"
45
46RealViewCtrl::RealViewCtrl(Params *p)
46 : BasicPioDevice(p, 0xD4), flags(0)
47 : BasicPioDevice(p, 0xD4), flags(0), scData(0)
47{
48}
49
50Tick
51RealViewCtrl::read(PacketPtr pkt)
52{
53 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
54 assert(pkt->getSize() == 4);

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100 pkt->set<uint32_t>(flags);
101 break;
102 case IdReg:
103 pkt->set<uint32_t>(params()->idreg);
104 break;
105 case CfgStat:
106 pkt->set<uint32_t>(1);
107 break;
48{
49}
50
51Tick
52RealViewCtrl::read(PacketPtr pkt)
53{
54 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
55 assert(pkt->getSize() == 4);

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101 pkt->set<uint32_t>(flags);
102 break;
103 case IdReg:
104 pkt->set<uint32_t>(params()->idreg);
105 break;
106 case CfgStat:
107 pkt->set<uint32_t>(1);
108 break;
109 case CfgData:
110 pkt->set<uint32_t>(scData);
111 DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
112 break;
113 case CfgCtrl:
114 pkt->set<uint32_t>(0); // not busy
115 DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
116 break;
108 default:
109 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
110 daddr);
117 default:
118 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
119 daddr);
120 pkt->set<uint32_t>(0);
111 break;
112 }
113 pkt->makeAtomicResponse();
114 return pioDelay;
115
116}
117
118Tick

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134 sysLock.lockVal = pkt->get<uint16_t>();
135 break;
136 case Flags:
137 flags = pkt->get<uint32_t>();
138 break;
139 case FlagsClr:
140 flags = 0;
141 break;
121 break;
122 }
123 pkt->makeAtomicResponse();
124 return pioDelay;
125
126}
127
128Tick

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144 sysLock.lockVal = pkt->get<uint16_t>();
145 break;
146 case Flags:
147 flags = pkt->get<uint32_t>();
148 break;
149 case FlagsClr:
150 flags = 0;
151 break;
152 case CfgData:
153 scData = pkt->get<uint32_t>();
154 break;
155 case CfgCtrl: {
156 // A request is being submitted to read/write the system control
157 // registers. See
158 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
159 // For now, model as much of the OSC regs (can't find docs) as Linux
160 // seems to require (can't find docs); some clocks are deemed to be 0,
161 // giving all kinds of /0 problems booting Linux 3.9. Return a
162 // vaguely plausible number within the range the device trees state:
163 uint32_t data = pkt->get<uint32_t>();
164 uint16_t dev = bits(data, 11, 0);
165 uint8_t pos = bits(data, 15, 12);
166 uint8_t site = bits(data, 17, 16);
167 uint8_t func = bits(data, 25, 20);
168 uint8_t dcc = bits(data, 29, 26);
169 bool wr = bits(data, 30);
170 bool start = bits(data, 31);
171
172 if (start) {
173 if (wr) {
174 warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n",
175 scData, dcc, site, pos, func, dev);
176 // Only really support reading, for now!
177 } else {
178 // Only deal with function 1 (oscillators) so far!
179 if (dcc != 0 || pos != 0 || func != 1) {
180 warn("SCReg: read from unknown area "
181 "(dcc %d:site%d:pos%d:fn%d:dev%d)\n",
182 dcc, site, pos, func, dev);
183 } else {
184 switch (site) {
185 case 0: { // Motherboard regs
186 switch(dev) {
187 case 0: // MCC clk
188 scData = 25000000;
189 break;
190 case 1: // CLCD clk
191 scData = 25000000;
192 break;
193 case 2: // PeriphClk 24MHz
194 scData = 24000000;
195 break;
196 default:
197 scData = 0;
198 warn("SCReg: read from unknown dev %d "
199 "(site%d:pos%d:fn%d)\n",
200 dev, site, pos, func);
201 }
202 } break;
203 case 1: { // Coretile 1 regs
204 switch(dev) {
205 case 0: // CPU PLL ref
206 scData = 50000000;
207 break;
208 case 4: // Muxed AXI master clock
209 scData = 40000000;
210 break;
211 case 5: // HDLCD clk
212 scData = 50000000;
213 break;
214 case 6: // SMB clock
215 scData = 35000000;
216 break;
217 case 7: // SYS PLL (also used for pl011 UART!)
218 scData = 40000000;
219 break;
220 case 8: // DDR PLL 40MHz fixed
221 scData = 40000000;
222 break;
223 default:
224 scData = 0;
225 warn("SCReg: read from unknown dev %d "
226 "(site%d:pos%d:fn%d)\n",
227 dev, site, pos, func);
228 }
229 } break;
230 default:
231 warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n",
232 site, pos, func, dev);
233 }
234 DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data);
235 }
236 }
237 } else {
238 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data);
239 }
240 } break;
241 case CfgStat: // Weird to write this
142 default:
242 default:
143 warn("Tried to write RVIO at offset %#x that doesn't exist\n",
144 daddr);
243 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
244 daddr, pkt->get<uint32_t>());
145 break;
146 }
147 pkt->makeAtomicResponse();
148 return pioDelay;
149}
150
151void
152RealViewCtrl::serialize(std::ostream &os)

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246 }
247 pkt->makeAtomicResponse();
248 return pioDelay;
249}
250
251void
252RealViewCtrl::serialize(std::ostream &os)

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