rv_ctrl.cc (12078:6bbedad2eb30) rv_ctrl.cc (13230:2988dc5d1d6f)
1/*
2 * Copyright (c) 2010,2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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56RealViewCtrl::read(PacketPtr pkt)
57{
58 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
59 assert(pkt->getSize() == 4);
60 Addr daddr = pkt->getAddr() - pioAddr;
61
62 switch(daddr) {
63 case ProcId0:
1/*
2 * Copyright (c) 2010,2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 47 unchanged lines hidden (view full) ---

56RealViewCtrl::read(PacketPtr pkt)
57{
58 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
59 assert(pkt->getSize() == 4);
60 Addr daddr = pkt->getAddr() - pioAddr;
61
62 switch(daddr) {
63 case ProcId0:
64 pkt->set(params()->proc_id0);
64 pkt->setLE(params()->proc_id0);
65 break;
66 case ProcId1:
65 break;
66 case ProcId1:
67 pkt->set(params()->proc_id1);
67 pkt->setLE(params()->proc_id1);
68 break;
69 case Clock24:
70 Tick clk;
71 clk = SimClock::Float::MHz * curTick() * 24;
68 break;
69 case Clock24:
70 Tick clk;
71 clk = SimClock::Float::MHz * curTick() * 24;
72 pkt->set((uint32_t)(clk));
72 pkt->setLE((uint32_t)(clk));
73 break;
74 case Clock100:
75 Tick clk100;
76 clk100 = SimClock::Float::MHz * curTick() * 100;
73 break;
74 case Clock100:
75 Tick clk100;
76 clk100 = SimClock::Float::MHz * curTick() * 100;
77 pkt->set((uint32_t)(clk100));
77 pkt->setLE((uint32_t)(clk100));
78 break;
79 case Flash:
78 break;
79 case Flash:
80 pkt->set(0);
80 pkt->setLE<uint32_t>(0);
81 break;
82 case Clcd:
81 break;
82 case Clcd:
83 pkt->set(0x00001F00);
83 pkt->setLE<uint32_t>(0x00001F00);
84 break;
85 case Osc0:
84 break;
85 case Osc0:
86 pkt->set(0x00012C5C);
86 pkt->setLE<uint32_t>(0x00012C5C);
87 break;
88 case Osc1:
87 break;
88 case Osc1:
89 pkt->set(0x00002CC0);
89 pkt->setLE<uint32_t>(0x00002CC0);
90 break;
91 case Osc2:
90 break;
91 case Osc2:
92 pkt->set(0x00002C75);
92 pkt->setLE<uint32_t>(0x00002C75);
93 break;
94 case Osc3:
93 break;
94 case Osc3:
95 pkt->set(0x00020211);
95 pkt->setLE<uint32_t>(0x00020211);
96 break;
97 case Osc4:
96 break;
97 case Osc4:
98 pkt->set(0x00002C75);
98 pkt->setLE<uint32_t>(0x00002C75);
99 break;
100 case Lock:
99 break;
100 case Lock:
101 pkt->set(sysLock);
101 pkt->setLE<uint32_t>(sysLock);
102 break;
103 case Flags:
102 break;
103 case Flags:
104 pkt->set(flags);
104 pkt->setLE<uint32_t>(flags);
105 break;
106 case IdReg:
105 break;
106 case IdReg:
107 pkt->set(params()->idreg);
107 pkt->setLE<uint32_t>(params()->idreg);
108 break;
109 case CfgStat:
108 break;
109 case CfgStat:
110 pkt->set(1);
110 pkt->setLE<uint32_t>(1);
111 break;
112 case CfgData:
111 break;
112 case CfgData:
113 pkt->set(scData);
113 pkt->setLE<uint32_t>(scData);
114 DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
115 break;
116 case CfgCtrl:
114 DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
115 break;
116 case CfgCtrl:
117 pkt->set(0); // not busy
117 pkt->setLE<uint32_t>(0); // not busy
118 DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
119 break;
120 default:
121 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
122 daddr);
118 DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
119 break;
120 default:
121 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
122 daddr);
123 pkt->set(0);
123 pkt->setLE<uint32_t>(0);
124 break;
125 }
126 pkt->makeAtomicResponse();
127 return pioDelay;
128
129}
130
131Tick

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139 case Clcd:
140 case Osc0:
141 case Osc1:
142 case Osc2:
143 case Osc3:
144 case Osc4:
145 break;
146 case Lock:
124 break;
125 }
126 pkt->makeAtomicResponse();
127 return pioDelay;
128
129}
130
131Tick

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139 case Clcd:
140 case Osc0:
141 case Osc1:
142 case Osc2:
143 case Osc3:
144 case Osc4:
145 break;
146 case Lock:
147 sysLock.lockVal = pkt->get();
147 sysLock.lockVal = pkt->getLE<uint16_t>();
148 break;
149 case ResetCtl:
150 // Ignore writes to reset control
151 warn_once("Ignoring write to reset control\n");
152 break;
153 case Flags:
148 break;
149 case ResetCtl:
150 // Ignore writes to reset control
151 warn_once("Ignoring write to reset control\n");
152 break;
153 case Flags:
154 flags = pkt->get();
154 flags = pkt->getLE<uint32_t>();
155 break;
156 case FlagsClr:
157 flags = 0;
158 break;
159 case CfgData:
155 break;
156 case FlagsClr:
157 flags = 0;
158 break;
159 case CfgData:
160 scData = pkt->get();
160 scData = pkt->getLE<uint32_t>();
161 break;
162 case CfgCtrl: {
163 // A request is being submitted to read/write the system control
164 // registers. See
165 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
161 break;
162 case CfgCtrl: {
163 // A request is being submitted to read/write the system control
164 // registers. See
165 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
166 CfgCtrlReg req = pkt->get();
166 CfgCtrlReg req = pkt->getLE<uint32_t>();
167 if (!req.start) {
168 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
169 req);
170 break;
171 }
172
173 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
174 if (it_dev == devices.end()) {

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190 scData = dev.read();
191 DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n",
192 scData, req);
193 }
194 } break;
195 case CfgStat: // Weird to write this
196 default:
197 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
167 if (!req.start) {
168 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
169 req);
170 break;
171 }
172
173 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
174 if (it_dev == devices.end()) {

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190 scData = dev.read();
191 DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n",
192 scData, req);
193 }
194 } break;
195 case CfgStat: // Weird to write this
196 default:
197 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
198 daddr, pkt->get());
198 daddr, pkt->getLE<uint32_t>());
199 break;
200 }
201 pkt->makeAtomicResponse();
202 return pioDelay;
203}
204
205void
206RealViewCtrl::serialize(CheckpointOut &cp) const

--- 129 unchanged lines hidden --- 		199 break;
200 }
201 pkt->makeAtomicResponse();
202 return pioDelay;
203}
204
205void
206RealViewCtrl::serialize(CheckpointOut &cp) const

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