1/* 2 * Copyright (c) 2010,2013,2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39
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40#include "dev/arm/rv_ctrl.hh" 41 |
42#include "base/trace.hh" 43#include "debug/RVCTRL.hh"
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42#include "dev/arm/rv_ctrl.hh"
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44#include "mem/packet.hh" 45#include "mem/packet_access.hh"
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46#include "sim/power/thermal_model.hh" 47#include "sim/system.hh" |
48#include "sim/voltage_domain.hh" 49 50RealViewCtrl::RealViewCtrl(Params *p) 51 : BasicPioDevice(p, 0xD4), flags(0), scData(0) 52{ 53} 54 55Tick 56RealViewCtrl::read(PacketPtr pkt) 57{ 58 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 59 assert(pkt->getSize() == 4); 60 Addr daddr = pkt->getAddr() - pioAddr; 61 62 switch(daddr) { 63 case ProcId0: 64 pkt->set(params()->proc_id0); 65 break; 66 case ProcId1: 67 pkt->set(params()->proc_id1); 68 break; 69 case Clock24: 70 Tick clk; 71 clk = SimClock::Float::MHz * curTick() * 24; 72 pkt->set((uint32_t)(clk)); 73 break; 74 case Clock100: 75 Tick clk100; 76 clk100 = SimClock::Float::MHz * curTick() * 100; 77 pkt->set((uint32_t)(clk100)); 78 break; 79 case Flash: 80 pkt->set<uint32_t>(0); 81 break; 82 case Clcd: 83 pkt->set<uint32_t>(0x00001F00); 84 break; 85 case Osc0: 86 pkt->set<uint32_t>(0x00012C5C); 87 break; 88 case Osc1: 89 pkt->set<uint32_t>(0x00002CC0); 90 break; 91 case Osc2: 92 pkt->set<uint32_t>(0x00002C75); 93 break; 94 case Osc3: 95 pkt->set<uint32_t>(0x00020211); 96 break; 97 case Osc4: 98 pkt->set<uint32_t>(0x00002C75); 99 break; 100 case Lock: 101 pkt->set<uint32_t>(sysLock); 102 break; 103 case Flags: 104 pkt->set<uint32_t>(flags); 105 break; 106 case IdReg: 107 pkt->set<uint32_t>(params()->idreg); 108 break; 109 case CfgStat: 110 pkt->set<uint32_t>(1); 111 break; 112 case CfgData: 113 pkt->set<uint32_t>(scData); 114 DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData); 115 break; 116 case CfgCtrl: 117 pkt->set<uint32_t>(0); // not busy 118 DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n"); 119 break; 120 default: 121 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", 122 daddr); 123 pkt->set<uint32_t>(0); 124 break; 125 } 126 pkt->makeAtomicResponse(); 127 return pioDelay; 128 129} 130 131Tick 132RealViewCtrl::write(PacketPtr pkt) 133{ 134 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 135 136 Addr daddr = pkt->getAddr() - pioAddr; 137 switch (daddr) { 138 case Flash: 139 case Clcd: 140 case Osc0: 141 case Osc1: 142 case Osc2: 143 case Osc3: 144 case Osc4: 145 break; 146 case Lock: 147 sysLock.lockVal = pkt->get<uint16_t>(); 148 break; 149 case Flags: 150 flags = pkt->get<uint32_t>(); 151 break; 152 case FlagsClr: 153 flags = 0; 154 break; 155 case CfgData: 156 scData = pkt->get<uint32_t>(); 157 break; 158 case CfgCtrl: { 159 // A request is being submitted to read/write the system control 160 // registers. See 161 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html 162 CfgCtrlReg req = pkt->get<uint32_t>(); 163 if (!req.start) { 164 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", 165 req); 166 break; 167 } 168 169 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK)); 170 if (it_dev == devices.end()) { 171 warn_once("SCReg: Access to unknown device " 172 "dcc%d:site%d:pos%d:fn%d:dev%d\n", 173 req.dcc, req.site, req.pos, req.func, req.dev); 174 break; 175 } 176 177 // Service the request as a read or write depending on the 178 // wr bit in the control register. 179 Device &dev(*it_dev->second); 180 if (req.wr) { 181 DPRINTF(RVCTRL, "SCReg: Writing %#x (ctrlWr %#x)\n", 182 scData, req); 183 dev.write(scData); 184 185 } else { 186 scData = dev.read(); 187 DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n", 188 scData, req); 189 } 190 } break; 191 case CfgStat: // Weird to write this 192 default: 193 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", 194 daddr, pkt->get<uint32_t>()); 195 break; 196 } 197 pkt->makeAtomicResponse(); 198 return pioDelay; 199} 200 201void 202RealViewCtrl::serialize(CheckpointOut &cp) const 203{ 204 SERIALIZE_SCALAR(flags); 205} 206 207void 208RealViewCtrl::unserialize(CheckpointIn &cp) 209{ 210 UNSERIALIZE_SCALAR(flags); 211} 212 213void 214RealViewCtrl::registerDevice(DeviceFunc func, uint8_t site, uint8_t pos, 215 uint8_t dcc, uint16_t dev, 216 Device *handler) 217{ 218 CfgCtrlReg addr = 0; 219 addr.func = func; 220 addr.site = site; 221 addr.pos = pos; 222 addr.dcc = dcc; 223 addr.dev = dev; 224 225 if (devices.find(addr) != devices.end()) { 226 fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d " 227 "already registered.", 228 addr.dcc, addr.site, addr.pos, addr.func, addr.dev); 229 } 230 231 devices[addr] = handler; 232} 233 234 235RealViewOsc::RealViewOsc(RealViewOscParams *p) 236 : ClockDomain(p, p->voltage_domain), 237 RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_OSC, 238 p->site, p->position, p->dcc, p->device) 239{ 240 if (SimClock::Float::s / p->freq > UINT32_MAX) { 241 fatal("Oscillator frequency out of range: %f\n", 242 SimClock::Float::s / p->freq / 1E6); 243 } 244 245 _clockPeriod = p->freq; 246} 247 248void 249RealViewOsc::startup() 250{ 251 // Tell dependent object to set their clock frequency 252 for (auto m : members) 253 m->updateClockPeriod(); 254} 255 256void 257RealViewOsc::serialize(CheckpointOut &cp) const 258{ 259 SERIALIZE_SCALAR(_clockPeriod); 260} 261 262void 263RealViewOsc::unserialize(CheckpointIn &cp) 264{ 265 UNSERIALIZE_SCALAR(_clockPeriod); 266} 267 268void 269RealViewOsc::clockPeriod(Tick clock_period) 270{ 271 panic_if(clock_period == 0, "%s has a clock period of zero\n", name()); 272 273 // Align all members to the current tick 274 for (auto m : members) 275 m->updateClockPeriod(); 276 277 _clockPeriod = clock_period; 278 279 // inform any derived clocks they need to updated their period 280 for (auto m : children) 281 m->updateClockPeriod(); 282} 283 284uint32_t 285RealViewOsc::read() const 286{ 287 const uint32_t freq(SimClock::Float::s / _clockPeriod); 288 DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6); 289 return freq; 290} 291 292void 293RealViewOsc::write(uint32_t freq) 294{ 295 DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6); 296 clockPeriod(SimClock::Float::s / freq); 297} 298
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299uint32_t 300RealViewTemperatureSensor::read() const 301{ 302 // Temperature reported in uC 303 ThermalModel * tm = system->getThermalModel(); 304 if (tm) { 305 double t = tm->getTemp(); 306 if (t < 0) 307 warn("Temperature below zero!\n"); 308 return fmax(0, t) * 1000000; 309 } |
310
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311 // Report a dummy 25 degrees temperature 312 return 25000000; 313} |
314 315RealViewCtrl * 316RealViewCtrlParams::create() 317{ 318 return new RealViewCtrl(this); 319} 320 321RealViewOsc * 322RealViewOscParams::create() 323{ 324 return new RealViewOsc(this); 325}
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326 327RealViewTemperatureSensor * 328RealViewTemperatureSensorParams::create() 329{ 330 return new RealViewTemperatureSensor(this); 331} |
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