rv_ctrl.cc (10905:a6ca6831e775) | rv_ctrl.cc (11011:2ca6c68fdd6c) |
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1/* | 1/* |
2 * Copyright (c) 2010,2013 ARM Limited | 2 * Copyright (c) 2010,2013,2015 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 26 unchanged lines hidden (view full) --- 37 * Authors: Ali Saidi 38 */ 39 40#include "base/trace.hh" 41#include "debug/RVCTRL.hh" 42#include "dev/arm/rv_ctrl.hh" 43#include "mem/packet.hh" 44#include "mem/packet_access.hh" | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 26 unchanged lines hidden (view full) --- 37 * Authors: Ali Saidi 38 */ 39 40#include "base/trace.hh" 41#include "debug/RVCTRL.hh" 42#include "dev/arm/rv_ctrl.hh" 43#include "mem/packet.hh" 44#include "mem/packet_access.hh" |
45#include "sim/voltage_domain.hh" |
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45 46RealViewCtrl::RealViewCtrl(Params *p) 47 : BasicPioDevice(p, 0xD4), flags(0), scData(0) 48{ 49} 50 51Tick 52RealViewCtrl::read(PacketPtr pkt) --- 97 unchanged lines hidden (view full) --- 150 break; 151 case CfgData: 152 scData = pkt->get<uint32_t>(); 153 break; 154 case CfgCtrl: { 155 // A request is being submitted to read/write the system control 156 // registers. See 157 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html | 46 47RealViewCtrl::RealViewCtrl(Params *p) 48 : BasicPioDevice(p, 0xD4), flags(0), scData(0) 49{ 50} 51 52Tick 53RealViewCtrl::read(PacketPtr pkt) --- 97 unchanged lines hidden (view full) --- 151 break; 152 case CfgData: 153 scData = pkt->get<uint32_t>(); 154 break; 155 case CfgCtrl: { 156 // A request is being submitted to read/write the system control 157 // registers. See 158 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html |
158 // For now, model as much of the OSC regs (can't find docs) as Linux 159 // seems to require (can't find docs); some clocks are deemed to be 0, 160 // giving all kinds of /0 problems booting Linux 3.9. Return a 161 // vaguely plausible number within the range the device trees state: 162 uint32_t data = pkt->get<uint32_t>(); 163 uint16_t dev = bits(data, 11, 0); 164 uint8_t pos = bits(data, 15, 12); 165 uint8_t site = bits(data, 17, 16); 166 uint8_t func = bits(data, 25, 20); 167 uint8_t dcc = bits(data, 29, 26); 168 bool wr = bits(data, 30); 169 bool start = bits(data, 31); | 159 CfgCtrlReg req = pkt->get<uint32_t>(); 160 if (!req.start) { 161 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", 162 req); 163 break; 164 } |
170 | 165 |
171 if (start) { 172 if (wr) { 173 warn_once("SCReg: Writing %#x to dcc%d:site%d:pos%d:fn%d:dev%d\n", 174 scData, dcc, site, pos, func, dev); 175 // Only really support reading, for now! 176 } else { 177 // Only deal with function 1 (oscillators) so far! 178 if (dcc != 0 || pos != 0 || func != 1) { 179 warn("SCReg: read from unknown area " 180 "(dcc %d:site%d:pos%d:fn%d:dev%d)\n", 181 dcc, site, pos, func, dev); 182 } else { 183 switch (site) { 184 case 0: { // Motherboard regs 185 switch(dev) { 186 case 0: // MCC clk 187 scData = 25000000; 188 break; 189 case 1: // CLCD clk 190 scData = 25000000; 191 break; 192 case 2: // PeriphClk 24MHz 193 scData = 24000000; 194 break; 195 default: 196 scData = 0; 197 warn("SCReg: read from unknown dev %d " 198 "(site%d:pos%d:fn%d)\n", 199 dev, site, pos, func); 200 } 201 } break; 202 case 1: { // Coretile 1 regs 203 switch(dev) { 204 case 0: // CPU PLL ref 205 scData = 50000000; 206 break; 207 case 4: // Muxed AXI master clock 208 scData = 40000000; 209 break; 210 case 5: // HDLCD clk 211 scData = 50000000; 212 break; 213 case 6: // SMB clock 214 scData = 35000000; 215 break; 216 case 7: // SYS PLL (also used for pl011 UART!) 217 scData = 40000000; 218 break; 219 case 8: // DDR PLL 40MHz fixed 220 scData = 40000000; 221 break; 222 default: 223 scData = 0; 224 warn("SCReg: read from unknown dev %d " 225 "(site%d:pos%d:fn%d)\n", 226 dev, site, pos, func); 227 } 228 } break; 229 default: 230 warn("SCReg: Read from unknown site %d (pos%d:fn%d:dev%d)\n", 231 site, pos, func, dev); 232 } 233 DPRINTF(RVCTRL, "SCReg: Will read %#x (ctrlWr %#x)\n", scData, data); 234 } 235 } | 166 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK)); 167 if (it_dev == devices.end()) { 168 warn_once("SCReg: Access to unknown device " 169 "dcc%d:site%d:pos%d:fn%d:dev%d\n", 170 req.dcc, req.site, req.pos, req.func, req.dev); 171 break; 172 } 173 174 // Service the request as a read or write depending on the 175 // wr bit in the control register. 176 Device &dev(*it_dev->second); 177 if (req.wr) { 178 DPRINTF(RVCTRL, "SCReg: Writing %#x (ctrlWr %#x)\n", 179 scData, req); 180 dev.write(scData); 181 |
236 } else { | 182 } else { |
237 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", data); | 183 scData = dev.read(); 184 DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n", 185 scData, req); |
238 } 239 } break; 240 case CfgStat: // Weird to write this 241 default: 242 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", 243 daddr, pkt->get<uint32_t>()); 244 break; 245 } --- 8 unchanged lines hidden (view full) --- 254} 255 256void 257RealViewCtrl::unserialize(CheckpointIn &cp) 258{ 259 UNSERIALIZE_SCALAR(flags); 260} 261 | 186 } 187 } break; 188 case CfgStat: // Weird to write this 189 default: 190 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", 191 daddr, pkt->get<uint32_t>()); 192 break; 193 } --- 8 unchanged lines hidden (view full) --- 202} 203 204void 205RealViewCtrl::unserialize(CheckpointIn &cp) 206{ 207 UNSERIALIZE_SCALAR(flags); 208} 209 |
210void 211RealViewCtrl::registerDevice(DeviceFunc func, uint8_t site, uint8_t pos, 212 uint8_t dcc, uint16_t dev, 213 Device *handler) 214{ 215 CfgCtrlReg addr = 0; 216 addr.func = func; 217 addr.site = site; 218 addr.pos = pos; 219 addr.dcc = dcc; 220 addr.dev = dev; 221 222 if (devices.find(addr) != devices.end()) { 223 fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d " 224 "already registered.", 225 addr.dcc, addr.site, addr.pos, addr.func, addr.dev); 226 } 227 228 devices[addr] = handler; 229} 230 231 232RealViewOsc::RealViewOsc(RealViewOscParams *p) 233 : ClockDomain(p, p->voltage_domain), 234 RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_OSC, 235 p->site, p->position, p->dcc, p->device) 236{ 237 if (SimClock::Float::s / p->freq > UINT32_MAX) { 238 fatal("Oscillator frequency out of range: %f\n", 239 SimClock::Float::s / p->freq / 1E6); 240 } 241 242 _clockPeriod = p->freq; 243} 244 245void 246RealViewOsc::startup() 247{ 248 // Tell dependent object to set their clock frequency 249 for (auto m : members) 250 m->updateClockPeriod(); 251} 252 253void 254RealViewOsc::serialize(CheckpointOut &cp) const 255{ 256 SERIALIZE_SCALAR(_clockPeriod); 257} 258 259void 260RealViewOsc::unserialize(CheckpointIn &cp) 261{ 262 UNSERIALIZE_SCALAR(_clockPeriod); 263} 264 265void 266RealViewOsc::clockPeriod(Tick clock_period) 267{ 268 panic_if(clock_period == 0, "%s has a clock period of zero\n", name()); 269 270 // Align all members to the current tick 271 for (auto m : members) 272 m->updateClockPeriod(); 273 274 _clockPeriod = clock_period; 275 276 // inform any derived clocks they need to updated their period 277 for (auto m : children) 278 m->updateClockPeriod(); 279} 280 281uint32_t 282RealViewOsc::read() const 283{ 284 const uint32_t freq(SimClock::Float::s / _clockPeriod); 285 DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6); 286 return freq; 287} 288 289void 290RealViewOsc::write(uint32_t freq) 291{ 292 DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6); 293 clockPeriod(SimClock::Float::s / freq); 294} 295 296 297 |
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262RealViewCtrl * 263RealViewCtrlParams::create() 264{ 265 return new RealViewCtrl(this); 266} | 298RealViewCtrl * 299RealViewCtrlParams::create() 300{ 301 return new RealViewCtrl(this); 302} |
303 304RealViewOsc * 305RealViewOscParams::create() 306{ 307 return new RealViewOsc(this); 308} |
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