1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __DEV_ARM_RTC_PL310_HH__
41#define __DEV_ARM_RTC_PL310_HH__
42
43#include "dev/arm/amba_device.hh"
44#include "params/PL031.hh"
45
46/** @file
47 * This implements the ARM Primecell 031 RTC
48 */
49
50class PL031 : public AmbaIntDevice
51{
52 protected:
53 enum {
54 DataReg = 0x00,
55 MatchReg = 0x04,
56 LoadReg = 0x08,
57 ControlReg = 0x0C,
58 IntMask = 0x10,
59 RawISR = 0x14,
60 MaskedISR = 0x18,
61 IntClear = 0x1C,
62 };
63
64 /* Seconds since epoch that correspond to time simulation was started at the
65 * begining of simulation and is then updated if ever written. */
66 uint32_t timeVal;
67
68 /* Time when the timeVal register was written */
69 Tick lastWrittenTick;
70
71 /* Previous load value */
72 uint32_t loadVal;
73
74 /* RTC Match Value
75 * Cause an interrupt when this value hits counter
76 */
77 uint32_t matchVal;
78
79 /** If timer has caused an interrupt. This is irrespective of
80 * interrupt enable */
81 bool rawInt;
82
83 /** If the timer interrupt mask that is anded with the raw interrupt to
84 * generate a pending interrupt
85 */
86 bool maskInt;
87
88 /** If an interrupt is currently pending. Logical and of CTRL.intEnable
89 * and rawInt */
90 bool pendingInt;
91
92 /** Called when the counter reaches matches */
93 void counterMatch();
94 EventWrapper<PL031, &PL031::counterMatch> matchEvent;
95
96 /** Called to update the matchEvent when the load Value or match value are
97 * written.
98 */
99 void resyncMatch();
100
101 public:
102 typedef PL031Params Params;
103 const Params *
104 params() const
105 {
106 return dynamic_cast<const Params *>(_params);
107 }
108 /**
109 * The constructor for RealView just registers itself with the MMU.
110 * @param p params structure
111 */
112 PL031(Params *p);
113
114 /**
115 * Handle a read to the device
116 * @param pkt The memory request.
117 * @param data Where to put the data.
118 */
119 virtual Tick read(PacketPtr pkt);
120
121 /**
122 * Handle writes to the device
123 * @param pkt The memory request.
124 * @param data the data
125 */
126 virtual Tick write(PacketPtr pkt);
127
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __DEV_ARM_RTC_PL310_HH__
41#define __DEV_ARM_RTC_PL310_HH__
42
43#include "dev/arm/amba_device.hh"
44#include "params/PL031.hh"
45
46/** @file
47 * This implements the ARM Primecell 031 RTC
48 */
49
50class PL031 : public AmbaIntDevice
51{
52 protected:
53 enum {
54 DataReg = 0x00,
55 MatchReg = 0x04,
56 LoadReg = 0x08,
57 ControlReg = 0x0C,
58 IntMask = 0x10,
59 RawISR = 0x14,
60 MaskedISR = 0x18,
61 IntClear = 0x1C,
62 };
63
64 /* Seconds since epoch that correspond to time simulation was started at the
65 * begining of simulation and is then updated if ever written. */
66 uint32_t timeVal;
67
68 /* Time when the timeVal register was written */
69 Tick lastWrittenTick;
70
71 /* Previous load value */
72 uint32_t loadVal;
73
74 /* RTC Match Value
75 * Cause an interrupt when this value hits counter
76 */
77 uint32_t matchVal;
78
79 /** If timer has caused an interrupt. This is irrespective of
80 * interrupt enable */
81 bool rawInt;
82
83 /** If the timer interrupt mask that is anded with the raw interrupt to
84 * generate a pending interrupt
85 */
86 bool maskInt;
87
88 /** If an interrupt is currently pending. Logical and of CTRL.intEnable
89 * and rawInt */
90 bool pendingInt;
91
92 /** Called when the counter reaches matches */
93 void counterMatch();
94 EventWrapper<PL031, &PL031::counterMatch> matchEvent;
95
96 /** Called to update the matchEvent when the load Value or match value are
97 * written.
98 */
99 void resyncMatch();
100
101 public:
102 typedef PL031Params Params;
103 const Params *
104 params() const
105 {
106 return dynamic_cast<const Params *>(_params);
107 }
108 /**
109 * The constructor for RealView just registers itself with the MMU.
110 * @param p params structure
111 */
112 PL031(Params *p);
113
114 /**
115 * Handle a read to the device
116 * @param pkt The memory request.
117 * @param data Where to put the data.
118 */
119 virtual Tick read(PacketPtr pkt);
120
121 /**
122 * Handle writes to the device
123 * @param pkt The memory request.
124 * @param data the data
125 */
126 virtual Tick write(PacketPtr pkt);
127
|