| pl111.hh (9939:735d73e394d3) | pl111.hh (10546:288eb5ee4b00) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 186 unchanged lines hidden (view full) --- 195 196 /** Clock and signal polarity control register */ 197 TimingReg2 lcdTiming2; 198 199 /** Line end control register */ 200 TimingReg3 lcdTiming3; 201 202 /** Upper panel frame base address register */ | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 186 unchanged lines hidden (view full) --- 195 196 /** Clock and signal polarity control register */ 197 TimingReg2 lcdTiming2; 198 199 /** Line end control register */ 200 TimingReg3 lcdTiming3; 201 202 /** Upper panel frame base address register */ |
| 203 int lcdUpbase; | 203 uint32_t lcdUpbase; |
| 204 205 /** Lower panel frame base address register */ | 204 205 /** Lower panel frame base address register */ |
| 206 int lcdLpbase; | 206 uint32_t lcdLpbase; |
| 207 208 /** Control register */ 209 ControlReg lcdControl; 210 211 /** Interrupt mask set/clear register */ 212 InterruptReg lcdImsc; 213 214 /** Raw interrupt status register - const */ 215 InterruptReg lcdRis; 216 217 /** Masked interrupt status register */ 218 InterruptReg lcdMis; 219 220 /** 256x16-bit color palette registers 221 * 256 palette entries organized as 128 locations of two entries per word */ | 207 208 /** Control register */ 209 ControlReg lcdControl; 210 211 /** Interrupt mask set/clear register */ 212 InterruptReg lcdImsc; 213 214 /** Raw interrupt status register - const */ 215 InterruptReg lcdRis; 216 217 /** Masked interrupt status register */ 218 InterruptReg lcdMis; 219 220 /** 256x16-bit color palette registers 221 * 256 palette entries organized as 128 locations of two entries per word */ |
| 222 int lcdPalette[LcdPaletteSize]; | 222 uint32_t lcdPalette[LcdPaletteSize]; |
| 223 224 /** Cursor image RAM register 225 * 256-word wide values defining images overlaid by the hw cursor mechanism */ | 223 224 /** Cursor image RAM register 225 * 256-word wide values defining images overlaid by the hw cursor mechanism */ |
| 226 int cursorImage[CrsrImageSize]; | 226 uint32_t cursorImage[CrsrImageSize]; |
| 227 228 /** Cursor control register */ | 227 228 /** Cursor control register */ |
| 229 int clcdCrsrCtrl; | 229 uint32_t clcdCrsrCtrl; |
| 230 231 /** Cursor configuration register */ | 230 231 /** Cursor configuration register */ |
| 232 int clcdCrsrConfig; | 232 uint32_t clcdCrsrConfig; |
| 233 234 /** Cursor palette registers */ | 233 234 /** Cursor palette registers */ |
| 235 int clcdCrsrPalette0; 236 int clcdCrsrPalette1; | 235 uint32_t clcdCrsrPalette0; 236 uint32_t clcdCrsrPalette1; |
| 237 238 /** Cursor XY position register */ | 237 238 /** Cursor XY position register */ |
| 239 int clcdCrsrXY; | 239 uint32_t clcdCrsrXY; |
| 240 241 /** Cursor clip position register */ | 240 241 /** Cursor clip position register */ |
| 242 int clcdCrsrClip; | 242 uint32_t clcdCrsrClip; |
| 243 244 /** Cursor interrupt mask set/clear register */ 245 InterruptReg clcdCrsrImsc; 246 247 /** Cursor interrupt clear register */ 248 InterruptReg clcdCrsrIcr; 249 250 /** Cursor raw interrupt status register - const */ --- 34 unchanged lines hidden (view full) --- 285 286 /** Frame buffer max address */ 287 Addr maxAddr; 288 289 /** Frame buffer current address */ 290 Addr curAddr; 291 292 /** DMA FIFO watermark */ | 243 244 /** Cursor interrupt mask set/clear register */ 245 InterruptReg clcdCrsrImsc; 246 247 /** Cursor interrupt clear register */ 248 InterruptReg clcdCrsrIcr; 249 250 /** Cursor raw interrupt status register - const */ --- 34 unchanged lines hidden (view full) --- 285 286 /** Frame buffer max address */ 287 Addr maxAddr; 288 289 /** Frame buffer current address */ 290 Addr curAddr; 291 292 /** DMA FIFO watermark */ |
| 293 int waterMark; | 293 uint32_t waterMark; |
| 294 295 /** Number of pending dma reads */ | 294 295 /** Number of pending dma reads */ |
| 296 int dmaPendingNum; | 296 uint32_t dmaPendingNum; |
| 297 298 /** Send updated parameters to the vnc server */ 299 void updateVideoParams(); 300 301 /** DMA framebuffer read */ 302 void readFramebuffer(); 303 304 /** Generate dma framebuffer read event */ --- 74 unchanged lines hidden --- | 297 298 /** Send updated parameters to the vnc server */ 299 void updateVideoParams(); 300 301 /** DMA framebuffer read */ 302 void readFramebuffer(); 303 304 /** Generate dma framebuffer read event */ --- 74 unchanged lines hidden --- |