1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementiation of a PL011 UART
46 */
47
48#ifndef __DEV_ARM_PL011_H__
49#define __DEV_ARM_PL011_H__
50
51#include "base/bitfield.hh"
52#include "base/bitunion.hh"
53#include "dev/io_device.hh"
54#include "dev/uart.hh"
55#include "params/Pl011.hh"
56
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementiation of a PL011 UART
46 */
47
48#ifndef __DEV_ARM_PL011_H__
49#define __DEV_ARM_PL011_H__
50
51#include "base/bitfield.hh"
52#include "base/bitunion.hh"
53#include "dev/io_device.hh"
54#include "dev/uart.hh"
55#include "params/Pl011.hh"
56
|
58
59class Pl011 : public Uart
60{
61 protected:
62 static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
63 static const int UART_DR = 0x000;
64 static const int UART_FR = 0x018;
65 static const int UART_FR_CTS = 0x001;
66 static const int UART_FR_TXFE = 0x080;
67 static const int UART_FR_RXFE = 0x010;
68 static const int UART_IBRD = 0x024;
69 static const int UART_FBRD = 0x028;
70 static const int UART_LCRH = 0x02C;
71 static const int UART_CR = 0x030;
72 static const int UART_IFLS = 0x034;
73 static const int UART_IMSC = 0x038;
74 static const int UART_RIS = 0x03C;
75 static const int UART_MIS = 0x040;
76 static const int UART_ICR = 0x044;
77
78 uint16_t control;
79
80 /** fractional baud rate divisor. Not used for anything but reporting
81 * written value */
82 uint16_t fbrd;
83
84 /** integer baud rate divisor. Not used for anything but reporting
85 * written value */
86 uint16_t ibrd;
87
88 /** Line control register. Not used for anything but reporting
89 * written value */
90 uint16_t lcrh;
91
92 /** interrupt fifo level register. Not used for anything but reporting
93 * written value */
94 uint16_t ifls;
95
96 BitUnion16(INTREG)
97 Bitfield<0> rimim;
98 Bitfield<1> ctsmim;
99 Bitfield<2> dcdmim;
100 Bitfield<3> dsrmim;
101 Bitfield<4> rxim;
102 Bitfield<5> txim;
103 Bitfield<6> rtim;
104 Bitfield<7> feim;
105 Bitfield<8> peim;
106 Bitfield<9> beim;
107 Bitfield<10> oeim;
108 Bitfield<15,11> rsvd;
109 EndBitUnion(INTREG)
110
111 /** interrupt mask register. */
112 INTREG imsc;
113
114 /** raw interrupt status register */
115 INTREG rawInt;
116
117 /** Masked interrupt status register */
118 INTREG maskInt;
119
120 /** Interrupt number to generate */
121 int intNum;
122
123 /** Gic to use for interrupting */
| 58
59class Pl011 : public Uart
60{
61 protected:
62 static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
63 static const int UART_DR = 0x000;
64 static const int UART_FR = 0x018;
65 static const int UART_FR_CTS = 0x001;
66 static const int UART_FR_TXFE = 0x080;
67 static const int UART_FR_RXFE = 0x010;
68 static const int UART_IBRD = 0x024;
69 static const int UART_FBRD = 0x028;
70 static const int UART_LCRH = 0x02C;
71 static const int UART_CR = 0x030;
72 static const int UART_IFLS = 0x034;
73 static const int UART_IMSC = 0x038;
74 static const int UART_RIS = 0x03C;
75 static const int UART_MIS = 0x040;
76 static const int UART_ICR = 0x044;
77
78 uint16_t control;
79
80 /** fractional baud rate divisor. Not used for anything but reporting
81 * written value */
82 uint16_t fbrd;
83
84 /** integer baud rate divisor. Not used for anything but reporting
85 * written value */
86 uint16_t ibrd;
87
88 /** Line control register. Not used for anything but reporting
89 * written value */
90 uint16_t lcrh;
91
92 /** interrupt fifo level register. Not used for anything but reporting
93 * written value */
94 uint16_t ifls;
95
96 BitUnion16(INTREG)
97 Bitfield<0> rimim;
98 Bitfield<1> ctsmim;
99 Bitfield<2> dcdmim;
100 Bitfield<3> dsrmim;
101 Bitfield<4> rxim;
102 Bitfield<5> txim;
103 Bitfield<6> rtim;
104 Bitfield<7> feim;
105 Bitfield<8> peim;
106 Bitfield<9> beim;
107 Bitfield<10> oeim;
108 Bitfield<15,11> rsvd;
109 EndBitUnion(INTREG)
110
111 /** interrupt mask register. */
112 INTREG imsc;
113
114 /** raw interrupt status register */
115 INTREG rawInt;
116
117 /** Masked interrupt status register */
118 INTREG maskInt;
119
120 /** Interrupt number to generate */
121 int intNum;
122
123 /** Gic to use for interrupting */
|
125
126 /** Should the simulation end on an EOT */
127 bool endOnEOT;
128
129 /** Delay before interrupting */
130 Tick intDelay;
131
132 /** Function to generate interrupt */
133 void generateInterrupt();
134
135 /** Wrapper to create an event out of the thing */
136 EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
137
138 public:
139 typedef Pl011Params Params;
140 const Params *
141 params() const
142 {
143 return dynamic_cast<const Params *>(_params);
144 }
145 Pl011(const Params *p);
146
147 virtual Tick read(PacketPtr pkt);
148 virtual Tick write(PacketPtr pkt);
149
150 /**
151 * Inform the uart that there is data available.
152 */
153 virtual void dataAvailable();
154
155
156 /**
157 * Return if we have an interrupt pending
158 * @return interrupt status
159 * @todo fix me when implementation improves
160 */
161 virtual bool intStatus() { return false; }
162
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string §ion);
165
166};
167
168#endif //__DEV_ARM_PL011_H__
| 125
126 /** Should the simulation end on an EOT */
127 bool endOnEOT;
128
129 /** Delay before interrupting */
130 Tick intDelay;
131
132 /** Function to generate interrupt */
133 void generateInterrupt();
134
135 /** Wrapper to create an event out of the thing */
136 EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
137
138 public:
139 typedef Pl011Params Params;
140 const Params *
141 params() const
142 {
143 return dynamic_cast<const Params *>(_params);
144 }
145 Pl011(const Params *p);
146
147 virtual Tick read(PacketPtr pkt);
148 virtual Tick write(PacketPtr pkt);
149
150 /**
151 * Inform the uart that there is data available.
152 */
153 virtual void dataAvailable();
154
155
156 /**
157 * Return if we have an interrupt pending
158 * @return interrupt status
159 * @todo fix me when implementation improves
160 */
161 virtual bool intStatus() { return false; }
162
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string §ion);
165
166};
167
168#endif //__DEV_ARM_PL011_H__
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