| pl011.cc (7733:08d6a773d1b6) | pl011.cc (7823:dac01f14f20f) |
|---|---|
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 173 unchanged lines hidden (view full) --- 182 exitSimLoop("UART received EOT", 0); 183 184 term->out(data & 0xFF); 185 186 if (imsc.txim) { 187 DPRINTF(Uart, "TX int enabled, scheduling interruptt\n"); 188 rawInt.txim = 1; 189 if (!intEvent.scheduled()) | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 173 unchanged lines hidden (view full) --- 182 exitSimLoop("UART received EOT", 0); 183 184 term->out(data & 0xFF); 185 186 if (imsc.txim) { 187 DPRINTF(Uart, "TX int enabled, scheduling interruptt\n"); 188 rawInt.txim = 1; 189 if (!intEvent.scheduled()) |
| 190 schedule(intEvent, curTick + intDelay); | 190 schedule(intEvent, curTick() + intDelay); |
| 191 } 192 193 break; 194 case UART_CR: 195 control = data; 196 break; 197 case UART_IBRD: 198 ibrd = data; --- 13 unchanged lines hidden (view full) --- 212 if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim 213 || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) 214 panic("Unknown interrupt enabled\n"); 215 216 if (imsc.txim) { 217 DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); 218 rawInt.txim = 1; 219 if (!intEvent.scheduled()) | 191 } 192 193 break; 194 case UART_CR: 195 control = data; 196 break; 197 case UART_IBRD: 198 ibrd = data; --- 13 unchanged lines hidden (view full) --- 212 if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim 213 || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) 214 panic("Unknown interrupt enabled\n"); 215 216 if (imsc.txim) { 217 DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); 218 rawInt.txim = 1; 219 if (!intEvent.scheduled()) |
| 220 schedule(intEvent, curTick + intDelay); | 220 schedule(intEvent, curTick() + intDelay); |
| 221 } 222 223 break; 224 225 case UART_ICR: 226 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 227 rawInt = rawInt & ~data; 228 maskInt = rawInt & imsc; --- 18 unchanged lines hidden (view full) --- 247 /*@todo ignore the fifo, just say we have data now 248 * We might want to fix this, or we might not care */ 249 rawInt.rxim = 1; 250 rawInt.rtim = 1; 251 252 DPRINTF(Uart, "Data available, scheduling interrupt\n"); 253 254 if (!intEvent.scheduled()) | 221 } 222 223 break; 224 225 case UART_ICR: 226 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 227 rawInt = rawInt & ~data; 228 maskInt = rawInt & imsc; --- 18 unchanged lines hidden (view full) --- 247 /*@todo ignore the fifo, just say we have data now 248 * We might want to fix this, or we might not care */ 249 rawInt.rxim = 1; 250 rawInt.rtim = 1; 251 252 DPRINTF(Uart, "Data available, scheduling interrupt\n"); 253 254 if (!intEvent.scheduled()) |
| 255 schedule(intEvent, curTick + intDelay); | 255 schedule(intEvent, curTick() + intDelay); |
| 256} 257 258void 259Pl011::generateInterrupt() 260{ 261 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 262 imsc, rawInt, maskInt); 263 maskInt = imsc & rawInt; --- 65 unchanged lines hidden --- | 256} 257 258void 259Pl011::generateInterrupt() 260{ 261 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 262 imsc, rawInt, maskInt); 263 maskInt = imsc & rawInt; --- 65 unchanged lines hidden --- |