pl011.cc (12772:362544959c40) pl011.cc (13024:aa7890e43dab)
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87 clearInterrupts(UART_RXINTR | UART_RTINTR);
88 if (device->dataAvailable()) {
89 DPRINTF(Uart, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
91 dataAvailable();
92 }
93 }
94 break;
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 78 unchanged lines hidden (view full) ---

87 clearInterrupts(UART_RXINTR | UART_RTINTR);
88 if (device->dataAvailable()) {
89 DPRINTF(Uart, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
91 dataAvailable();
92 }
93 }
94 break;
95 case UART_RSR:
96 data = 0x0; // We never have errors
97 break;
95 case UART_FR:
96 data =
97 UART_FR_CTS | // Clear To Send
98 // Given we do not simulate a FIFO we are either empty or full.
99 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
100 UART_FR_TXFE; // TX FIFO empty
101
102 DPRINTF(Uart,

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200
201 device->writeData(data & 0xFF);
202 // We're supposed to clear TXINTR when this register is
203 // written to, however. since we're also infinitely fast, we
204 // need to immediately raise it again.
205 clearInterrupts(UART_TXINTR);
206 raiseInterrupts(UART_TXINTR);
207 break;
98 case UART_FR:
99 data =
100 UART_FR_CTS | // Clear To Send
101 // Given we do not simulate a FIFO we are either empty or full.
102 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
103 UART_FR_TXFE; // TX FIFO empty
104
105 DPRINTF(Uart,

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203
204 device->writeData(data & 0xFF);
205 // We're supposed to clear TXINTR when this register is
206 // written to, however. since we're also infinitely fast, we
207 // need to immediately raise it again.
208 clearInterrupts(UART_TXINTR);
209 raiseInterrupts(UART_TXINTR);
210 break;
211 case UART_ECR: // clears errors, ignore
212 break;
208 case UART_CR:
209 control = data;
210 break;
211 case UART_IBRD:
212 ibrd = data;
213 break;
214 case UART_FBRD:
215 fbrd = data;

--- 104 unchanged lines hidden --- 		213 case UART_CR:
214 control = data;
215 break;
216 case UART_IBRD:
217 ibrd = data;
218 break;
219 case UART_FBRD:
220 fbrd = data;

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