pl011.cc (12086:069c529a76fd) pl011.cc (12237:fdd8c4c63356)
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43
44#include "dev/arm/pl011.hh"
45
46#include "base/trace.hh"
47#include "debug/Checkpoint.hh"
48#include "debug/Uart.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/arm/base_gic.hh"
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43
44#include "dev/arm/pl011.hh"
45
46#include "base/trace.hh"
47#include "debug/Checkpoint.hh"
48#include "debug/Uart.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/arm/base_gic.hh"
51#include "dev/terminal.hh"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
54#include "params/Pl011.hh"
55#include "sim/sim_exit.hh"
56
57Pl011::Pl011(const Pl011Params *p)
58 : Uart(p, 0xfff),
59 intEvent([this]{ generateInterrupt(); }, name()),

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76 // use a temporary data since the uart registers are read/written with
77 // different size operations
78 //
79 uint32_t data = 0;
80
81 switch(daddr) {
82 case UART_DR:
83 data = 0;
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53#include "params/Pl011.hh"
54#include "sim/sim_exit.hh"
55
56Pl011::Pl011(const Pl011Params *p)
57 : Uart(p, 0xfff),
58 intEvent([this]{ generateInterrupt(); }, name()),

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75 // use a temporary data since the uart registers are read/written with
76 // different size operations
77 //
78 uint32_t data = 0;
79
80 switch(daddr) {
81 case UART_DR:
82 data = 0;
84 if (term->dataAvailable()) {
85 data = term->in();
83 if (device->dataAvailable()) {
84 data = device->readData();
86 // Since we don't simulate a FIFO for incoming data, we
87 // assume it's empty and clear RXINTR and RTINTR.
88 clearInterrupts(UART_RXINTR | UART_RTINTR);
85 // Since we don't simulate a FIFO for incoming data, we
86 // assume it's empty and clear RXINTR and RTINTR.
87 clearInterrupts(UART_RXINTR | UART_RTINTR);
89 if (term->dataAvailable()) {
88 if (device->dataAvailable()) {
90 DPRINTF(Uart, "Re-raising interrupt due to more data "
91 "after UART_DR read\n");
92 dataAvailable();
93 }
94 }
95 break;
96 case UART_FR:
97 data =
98 UART_FR_CTS | // Clear To Send
99 // Given we do not simulate a FIFO we are either empty or full.
89 DPRINTF(Uart, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
91 dataAvailable();
92 }
93 }
94 break;
95 case UART_FR:
96 data =
97 UART_FR_CTS | // Clear To Send
98 // Given we do not simulate a FIFO we are either empty or full.
100 (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
99 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
101 UART_FR_TXFE; // TX FIFO empty
102
103 DPRINTF(Uart,
104 "Reading FR register as %#x rawInt=0x%x "
105 "imsc=0x%x maskInt=0x%x\n",
106 data, rawInt, imsc, maskInt());
107 break;
108 case UART_CR:

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194 }
195
196
197 switch (daddr) {
198 case UART_DR:
199 if ((data & 0xFF) == 0x04 && endOnEOT)
200 exitSimLoop("UART received EOT", 0);
201
100 UART_FR_TXFE; // TX FIFO empty
101
102 DPRINTF(Uart,
103 "Reading FR register as %#x rawInt=0x%x "
104 "imsc=0x%x maskInt=0x%x\n",
105 data, rawInt, imsc, maskInt());
106 break;
107 case UART_CR:

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193 }
194
195
196 switch (daddr) {
197 case UART_DR:
198 if ((data & 0xFF) == 0x04 && endOnEOT)
199 exitSimLoop("UART received EOT", 0);
200
202 term->out(data & 0xFF);
201 device->writeData(data & 0xFF);
203 // We're supposed to clear TXINTR when this register is
204 // written to, however. since we're also infinitely fast, we
205 // need to immediately raise it again.
206 clearInterrupts(UART_TXINTR);
207 raiseInterrupts(UART_TXINTR);
208 break;
209 case UART_CR:
210 control = data;

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224 case UART_IMSC:
225 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
226 setInterruptMask(data);
227 break;
228
229 case UART_ICR:
230 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
231 clearInterrupts(data);
202 // We're supposed to clear TXINTR when this register is
203 // written to, however. since we're also infinitely fast, we
204 // need to immediately raise it again.
205 clearInterrupts(UART_TXINTR);
206 raiseInterrupts(UART_TXINTR);
207 break;
208 case UART_CR:
209 control = data;

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223 case UART_IMSC:
224 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
225 setInterruptMask(data);
226 break;
227
228 case UART_ICR:
229 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
230 clearInterrupts(data);
232 if (term->dataAvailable()) {
231 if (device->dataAvailable()) {
233 DPRINTF(Uart, "Re-raising interrupt due to more data after "
234 "UART_ICR write\n");
235 dataAvailable();
236 }
237 break;
238 default:
239 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
240 break;

--- 80 unchanged lines hidden --- 		232 DPRINTF(Uart, "Re-raising interrupt due to more data after "
233 "UART_ICR write\n");
234 dataAvailable();
235 }
236 break;
237 default:
238 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
239 break;

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