pl011.cc (11480:2af4c6a4f3f5) pl011.cc (11685:6281479f9713)
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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81 switch(daddr) {
82 case UART_DR:
83 data = 0;
84 if (term->dataAvailable()) {
85 data = term->in();
86 // Since we don't simulate a FIFO for incoming data, we
87 // assume it's empty and clear RXINTR and RTINTR.
88 clearInterrupts(UART_RXINTR | UART_RTINTR);
1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 72 unchanged lines hidden (view full) ---

81 switch(daddr) {
82 case UART_DR:
83 data = 0;
84 if (term->dataAvailable()) {
85 data = term->in();
86 // Since we don't simulate a FIFO for incoming data, we
87 // assume it's empty and clear RXINTR and RTINTR.
88 clearInterrupts(UART_RXINTR | UART_RTINTR);
89 if (term->dataAvailable()) {
90 DPRINTF(Uart, "Re-raising interrupt due to more data "
91 "after UART_DR read\n");
92 dataAvailable();
93 }
89 }
90 break;
91 case UART_FR:
92 data =
93 UART_FR_CTS | // Clear To Send
94 // Given we do not simulate a FIFO we are either empty or full.
95 (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
96 UART_FR_TXFE; // TX FIFO empty

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219 case UART_IMSC:
220 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
221 setInterruptMask(data);
222 break;
223
224 case UART_ICR:
225 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
226 clearInterrupts(data);
94 }
95 break;
96 case UART_FR:
97 data =
98 UART_FR_CTS | // Clear To Send
99 // Given we do not simulate a FIFO we are either empty or full.
100 (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
101 UART_FR_TXFE; // TX FIFO empty

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224 case UART_IMSC:
225 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
226 setInterruptMask(data);
227 break;
228
229 case UART_ICR:
230 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
231 clearInterrupts(data);
232 if (term->dataAvailable()) {
233 DPRINTF(Uart, "Re-raising interrupt due to more data after "
234 "UART_ICR write\n");
235 dataAvailable();
236 }
227 break;
228 default:
229 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
230 break;
231 }
232 pkt->makeAtomicResponse();
233 return pioDelay;
234}

--- 76 unchanged lines hidden --- 		237 break;
238 default:
239 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
240 break;
241 }
242 pkt->makeAtomicResponse();
243 return pioDelay;
244}

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