1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#include "base/trace.hh"
44#include "debug/Checkpoint.hh"
45#include "debug/Uart.hh"
46#include "dev/arm/amba_device.hh"
47#include "dev/arm/base_gic.hh"
48#include "dev/arm/pl011.hh"
49#include "dev/terminal.hh"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "sim/sim_exit.hh"
53
54Pl011::Pl011(const Params *p)
55 : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0),
56 rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
55 : Uart(p, 0xfff), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
56 imsc(0), rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic),
57 endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this)
58{
59 pioSize = 0xfff;
59}
60
61Tick
62Pl011::read(PacketPtr pkt)
63{
64 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
65
66 Addr daddr = pkt->getAddr() - pioAddr;
67 pkt->allocate();
68
69 DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
70
71 // use a temporary data since the uart registers are read/written with
72 // different size operations
73 //
74 uint32_t data = 0;
75
76 switch(daddr) {
77 case UART_DR:
78 data = 0;
79 if (term->dataAvailable())
80 data = term->in();
81 break;
82 case UART_FR:
83 // For now we're infintely fast, so TX is never full, always empty,
84 // always clear to send
85 data = UART_FR_TXFE | UART_FR_CTS;
86 if (!term->dataAvailable())
87 data |= UART_FR_RXFE;
88 DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n",
89 data, rawInt, imsc, maskInt);
90 break;
91 case UART_CR:
92 data = control;
93 break;
94 case UART_IBRD:
95 data = ibrd;
96 break;
97 case UART_FBRD:
98 data = fbrd;
99 break;
100 case UART_LCRH:
101 data = lcrh;
102 break;
103 case UART_IFLS:
104 data = ifls;
105 break;
106 case UART_IMSC:
107 data = imsc;
108 break;
109 case UART_RIS:
110 data = rawInt;
111 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
112 break;
113 case UART_MIS:
114 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt);
115 data = maskInt;
116 break;
117 default:
118 if (readId(pkt, AMBA_ID, pioAddr)) {
119 // Hack for variable size accesses
120 data = pkt->get<uint32_t>();
121 break;
122 }
123
124 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
125 break;
126 }
127
128 switch(pkt->getSize()) {
129 case 1:
130 pkt->set<uint8_t>(data);
131 break;
132 case 2:
133 pkt->set<uint16_t>(data);
134 break;
135 case 4:
136 pkt->set<uint32_t>(data);
137 break;
138 default:
139 panic("Uart read size too big?\n");
140 break;
141 }
142
143
144 pkt->makeAtomicResponse();
145 return pioDelay;
146}
147
148Tick
149Pl011::write(PacketPtr pkt)
150{
151
152 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
153
154 Addr daddr = pkt->getAddr() - pioAddr;
155
156 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
157 pkt->get<uint8_t>(), pkt->getSize());
158
159 // use a temporary data since the uart registers are read/written with
160 // different size operations
161 //
162 uint32_t data = 0;
163
164 switch(pkt->getSize()) {
165 case 1:
166 data = pkt->get<uint8_t>();
167 break;
168 case 2:
169 data = pkt->get<uint16_t>();
170 break;
171 case 4:
172 data = pkt->get<uint32_t>();
173 break;
174 default:
175 panic("Uart write size too big?\n");
176 break;
177 }
178
179
180 switch (daddr) {
181 case UART_DR:
182 if ((data & 0xFF) == 0x04 && endOnEOT)
183 exitSimLoop("UART received EOT", 0);
184
185 term->out(data & 0xFF);
186
187 //raw interrupt is set regardless of imsc.txim
188 rawInt.txim = 1;
189 if (imsc.txim) {
190 DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
191 if (!intEvent.scheduled())
192 schedule(intEvent, curTick() + intDelay);
193 }
194
195 break;
196 case UART_CR:
197 control = data;
198 break;
199 case UART_IBRD:
200 ibrd = data;
201 break;
202 case UART_FBRD:
203 fbrd = data;
204 break;
205 case UART_LCRH:
206 lcrh = data;
207 break;
208 case UART_IFLS:
209 ifls = data;
210 break;
211 case UART_IMSC:
212 imsc = data;
213
214 if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim
215 || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
216 panic("Unknown interrupt enabled\n");
217
218 if (imsc.txim) {
219 DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
220 rawInt.txim = 1;
221 if (!intEvent.scheduled())
222 schedule(intEvent, curTick() + intDelay);
223 }
224
225 break;
226
227 case UART_ICR:
228 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
229 rawInt = rawInt & ~data;
230 maskInt = rawInt & imsc;
231
232 DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt);
233
234 if (!maskInt)
235 gic->clearInt(intNum);
236
237 break;
238 default:
239 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
240 break;
241 }
242 pkt->makeAtomicResponse();
243 return pioDelay;
244}
245
246void
247Pl011::dataAvailable()
248{
249 /*@todo ignore the fifo, just say we have data now
250 * We might want to fix this, or we might not care */
251 rawInt.rxim = 1;
252 rawInt.rtim = 1;
253
254 DPRINTF(Uart, "Data available, scheduling interrupt\n");
255
256 if (!intEvent.scheduled())
257 schedule(intEvent, curTick() + intDelay);
258}
259
260void
261Pl011::generateInterrupt()
262{
263 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
264 imsc, rawInt, maskInt);
265 maskInt = imsc & rawInt;
266
267 if (maskInt.rxim || maskInt.rtim || maskInt.txim) {
268 gic->sendInt(intNum);
269 DPRINTF(Uart, " -- Generated\n");
270 }
271
272}
273
274
275
276void
277Pl011::serialize(std::ostream &os)
278{
279 DPRINTF(Checkpoint, "Serializing Arm PL011\n");
280 SERIALIZE_SCALAR(control);
281 SERIALIZE_SCALAR(fbrd);
282 SERIALIZE_SCALAR(ibrd);
283 SERIALIZE_SCALAR(lcrh);
284 SERIALIZE_SCALAR(ifls);
285
286 uint16_t imsc_serial = imsc;
287 SERIALIZE_SCALAR(imsc_serial);
288
289 uint16_t rawInt_serial = rawInt;
290 SERIALIZE_SCALAR(rawInt_serial);
291
292 uint16_t maskInt_serial = maskInt;
293 SERIALIZE_SCALAR(maskInt_serial);
294
295 SERIALIZE_SCALAR(endOnEOT);
296 SERIALIZE_SCALAR(intDelay);
297}
298
299void
300Pl011::unserialize(Checkpoint *cp, const std::string &section)
301{
302 DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
303
304 UNSERIALIZE_SCALAR(control);
305 UNSERIALIZE_SCALAR(fbrd);
306 UNSERIALIZE_SCALAR(ibrd);
307 UNSERIALIZE_SCALAR(lcrh);
308 UNSERIALIZE_SCALAR(ifls);
309
310 uint16_t imsc_serial;
311 UNSERIALIZE_SCALAR(imsc_serial);
312 imsc = imsc_serial;
313
314 uint16_t rawInt_serial;
315 UNSERIALIZE_SCALAR(rawInt_serial);
316 rawInt = rawInt_serial;
317
318 uint16_t maskInt_serial;
319 UNSERIALIZE_SCALAR(maskInt_serial);
320 maskInt = maskInt_serial;
321
322 UNSERIALIZE_SCALAR(endOnEOT);
323 UNSERIALIZE_SCALAR(intDelay);
324}
325
326Pl011 *
327Pl011Params::create()
328{
329 return new Pl011(this);
330}