1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Sandberg
42 */
43
44#include "dev/arm/pl011.hh"
45
46#include "base/trace.hh"
47#include "debug/Checkpoint.hh"
48#include "debug/Uart.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/arm/base_gic.hh"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53#include "params/Pl011.hh"
54#include "sim/sim_exit.hh"
55
56Pl011::Pl011(const Pl011Params *p)
| 1/*
2 * Copyright (c) 2010, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Sandberg
42 */
43
44#include "dev/arm/pl011.hh"
45
46#include "base/trace.hh"
47#include "debug/Checkpoint.hh"
48#include "debug/Uart.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/arm/base_gic.hh"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53#include "params/Pl011.hh"
54#include "sim/sim_exit.hh"
55
56Pl011::Pl011(const Pl011Params *p)
|
58 intEvent([this]{ generateInterrupt(); }, name()),
59 control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
60 imsc(0), rawInt(0),
61 gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
62 intDelay(p->int_delay)
63{
64}
65
66Tick
67Pl011::read(PacketPtr pkt)
68{
69 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
70
71 Addr daddr = pkt->getAddr() - pioAddr;
72
73 DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
74
75 // use a temporary data since the uart registers are read/written with
76 // different size operations
77 //
78 uint32_t data = 0;
79
80 switch(daddr) {
81 case UART_DR:
82 data = 0;
83 if (device->dataAvailable()) {
84 data = device->readData();
85 // Since we don't simulate a FIFO for incoming data, we
86 // assume it's empty and clear RXINTR and RTINTR.
87 clearInterrupts(UART_RXINTR | UART_RTINTR);
88 if (device->dataAvailable()) {
89 DPRINTF(Uart, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
91 dataAvailable();
92 }
93 }
94 break;
95 case UART_FR:
96 data =
97 UART_FR_CTS | // Clear To Send
98 // Given we do not simulate a FIFO we are either empty or full.
99 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
100 UART_FR_TXFE; // TX FIFO empty
101
102 DPRINTF(Uart,
103 "Reading FR register as %#x rawInt=0x%x "
104 "imsc=0x%x maskInt=0x%x\n",
105 data, rawInt, imsc, maskInt());
106 break;
107 case UART_CR:
108 data = control;
109 break;
110 case UART_IBRD:
111 data = ibrd;
112 break;
113 case UART_FBRD:
114 data = fbrd;
115 break;
116 case UART_LCRH:
117 data = lcrh;
118 break;
119 case UART_IFLS:
120 data = ifls;
121 break;
122 case UART_IMSC:
123 data = imsc;
124 break;
125 case UART_RIS:
126 data = rawInt;
127 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
128 break;
129 case UART_MIS:
130 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
131 data = maskInt();
132 break;
133 default:
134 if (readId(pkt, AMBA_ID, pioAddr)) {
135 // Hack for variable size accesses
136 data = pkt->get<uint32_t>();
137 break;
138 }
139
140 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
141 break;
142 }
143
144 switch(pkt->getSize()) {
145 case 1:
146 pkt->set<uint8_t>(data);
147 break;
148 case 2:
149 pkt->set<uint16_t>(data);
150 break;
151 case 4:
152 pkt->set<uint32_t>(data);
153 break;
154 default:
155 panic("Uart read size too big?\n");
156 break;
157 }
158
159
160 pkt->makeAtomicResponse();
161 return pioDelay;
162}
163
164Tick
165Pl011::write(PacketPtr pkt)
166{
167
168 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
169
170 Addr daddr = pkt->getAddr() - pioAddr;
171
172 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
173 pkt->get<uint8_t>(), pkt->getSize());
174
175 // use a temporary data since the uart registers are read/written with
176 // different size operations
177 //
178 uint32_t data = 0;
179
180 switch(pkt->getSize()) {
181 case 1:
182 data = pkt->get<uint8_t>();
183 break;
184 case 2:
185 data = pkt->get<uint16_t>();
186 break;
187 case 4:
188 data = pkt->get<uint32_t>();
189 break;
190 default:
191 panic("Uart write size too big?\n");
192 break;
193 }
194
195
196 switch (daddr) {
197 case UART_DR:
198 if ((data & 0xFF) == 0x04 && endOnEOT)
199 exitSimLoop("UART received EOT", 0);
200
201 device->writeData(data & 0xFF);
202 // We're supposed to clear TXINTR when this register is
203 // written to, however. since we're also infinitely fast, we
204 // need to immediately raise it again.
205 clearInterrupts(UART_TXINTR);
206 raiseInterrupts(UART_TXINTR);
207 break;
208 case UART_CR:
209 control = data;
210 break;
211 case UART_IBRD:
212 ibrd = data;
213 break;
214 case UART_FBRD:
215 fbrd = data;
216 break;
217 case UART_LCRH:
218 lcrh = data;
219 break;
220 case UART_IFLS:
221 ifls = data;
222 break;
223 case UART_IMSC:
224 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
225 setInterruptMask(data);
226 break;
227
228 case UART_ICR:
229 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
230 clearInterrupts(data);
231 if (device->dataAvailable()) {
232 DPRINTF(Uart, "Re-raising interrupt due to more data after "
233 "UART_ICR write\n");
234 dataAvailable();
235 }
236 break;
237 default:
238 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
239 break;
240 }
241 pkt->makeAtomicResponse();
242 return pioDelay;
243}
244
245void
246Pl011::dataAvailable()
247{
248 /*@todo ignore the fifo, just say we have data now
249 * We might want to fix this, or we might not care */
250 DPRINTF(Uart, "Data available, scheduling interrupt\n");
251 raiseInterrupts(UART_RXINTR | UART_RTINTR);
252}
253
254void
255Pl011::generateInterrupt()
256{
257 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
258 imsc, rawInt, maskInt());
259
260 if (maskInt()) {
261 gic->sendInt(intNum);
262 DPRINTF(Uart, " -- Generated\n");
263 }
264}
265
266void
267Pl011::setInterrupts(uint16_t ints, uint16_t mask)
268{
269 const bool old_ints(!!maskInt());
270
271 imsc = mask;
272 rawInt = ints;
273
274 if (!old_ints && maskInt()) {
275 if (!intEvent.scheduled())
276 schedule(intEvent, curTick() + intDelay);
277 } else if (old_ints && !maskInt()) {
278 gic->clearInt(intNum);
279 }
280}
281
282
283
284void
285Pl011::serialize(CheckpointOut &cp) const
286{
287 DPRINTF(Checkpoint, "Serializing Arm PL011\n");
288 SERIALIZE_SCALAR(control);
289 SERIALIZE_SCALAR(fbrd);
290 SERIALIZE_SCALAR(ibrd);
291 SERIALIZE_SCALAR(lcrh);
292 SERIALIZE_SCALAR(ifls);
293
294 // Preserve backwards compatibility by giving these silly names.
295 paramOut(cp, "imsc_serial", imsc);
296 paramOut(cp, "rawInt_serial", rawInt);
297}
298
299void
300Pl011::unserialize(CheckpointIn &cp)
301{
302 DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
303
304 UNSERIALIZE_SCALAR(control);
305 UNSERIALIZE_SCALAR(fbrd);
306 UNSERIALIZE_SCALAR(ibrd);
307 UNSERIALIZE_SCALAR(lcrh);
308 UNSERIALIZE_SCALAR(ifls);
309
310 // Preserve backwards compatibility by giving these silly names.
311 paramIn(cp, "imsc_serial", imsc);
312 paramIn(cp, "rawInt_serial", rawInt);
313}
314
315Pl011 *
316Pl011Params::create()
317{
318 return new Pl011(this);
319}
| 58 intEvent([this]{ generateInterrupt(); }, name()),
59 control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
60 imsc(0), rawInt(0),
61 gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
62 intDelay(p->int_delay)
63{
64}
65
66Tick
67Pl011::read(PacketPtr pkt)
68{
69 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
70
71 Addr daddr = pkt->getAddr() - pioAddr;
72
73 DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize());
74
75 // use a temporary data since the uart registers are read/written with
76 // different size operations
77 //
78 uint32_t data = 0;
79
80 switch(daddr) {
81 case UART_DR:
82 data = 0;
83 if (device->dataAvailable()) {
84 data = device->readData();
85 // Since we don't simulate a FIFO for incoming data, we
86 // assume it's empty and clear RXINTR and RTINTR.
87 clearInterrupts(UART_RXINTR | UART_RTINTR);
88 if (device->dataAvailable()) {
89 DPRINTF(Uart, "Re-raising interrupt due to more data "
90 "after UART_DR read\n");
91 dataAvailable();
92 }
93 }
94 break;
95 case UART_FR:
96 data =
97 UART_FR_CTS | // Clear To Send
98 // Given we do not simulate a FIFO we are either empty or full.
99 (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) |
100 UART_FR_TXFE; // TX FIFO empty
101
102 DPRINTF(Uart,
103 "Reading FR register as %#x rawInt=0x%x "
104 "imsc=0x%x maskInt=0x%x\n",
105 data, rawInt, imsc, maskInt());
106 break;
107 case UART_CR:
108 data = control;
109 break;
110 case UART_IBRD:
111 data = ibrd;
112 break;
113 case UART_FBRD:
114 data = fbrd;
115 break;
116 case UART_LCRH:
117 data = lcrh;
118 break;
119 case UART_IFLS:
120 data = ifls;
121 break;
122 case UART_IMSC:
123 data = imsc;
124 break;
125 case UART_RIS:
126 data = rawInt;
127 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt);
128 break;
129 case UART_MIS:
130 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt());
131 data = maskInt();
132 break;
133 default:
134 if (readId(pkt, AMBA_ID, pioAddr)) {
135 // Hack for variable size accesses
136 data = pkt->get<uint32_t>();
137 break;
138 }
139
140 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr);
141 break;
142 }
143
144 switch(pkt->getSize()) {
145 case 1:
146 pkt->set<uint8_t>(data);
147 break;
148 case 2:
149 pkt->set<uint16_t>(data);
150 break;
151 case 4:
152 pkt->set<uint32_t>(data);
153 break;
154 default:
155 panic("Uart read size too big?\n");
156 break;
157 }
158
159
160 pkt->makeAtomicResponse();
161 return pioDelay;
162}
163
164Tick
165Pl011::write(PacketPtr pkt)
166{
167
168 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
169
170 Addr daddr = pkt->getAddr() - pioAddr;
171
172 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr,
173 pkt->get<uint8_t>(), pkt->getSize());
174
175 // use a temporary data since the uart registers are read/written with
176 // different size operations
177 //
178 uint32_t data = 0;
179
180 switch(pkt->getSize()) {
181 case 1:
182 data = pkt->get<uint8_t>();
183 break;
184 case 2:
185 data = pkt->get<uint16_t>();
186 break;
187 case 4:
188 data = pkt->get<uint32_t>();
189 break;
190 default:
191 panic("Uart write size too big?\n");
192 break;
193 }
194
195
196 switch (daddr) {
197 case UART_DR:
198 if ((data & 0xFF) == 0x04 && endOnEOT)
199 exitSimLoop("UART received EOT", 0);
200
201 device->writeData(data & 0xFF);
202 // We're supposed to clear TXINTR when this register is
203 // written to, however. since we're also infinitely fast, we
204 // need to immediately raise it again.
205 clearInterrupts(UART_TXINTR);
206 raiseInterrupts(UART_TXINTR);
207 break;
208 case UART_CR:
209 control = data;
210 break;
211 case UART_IBRD:
212 ibrd = data;
213 break;
214 case UART_FBRD:
215 fbrd = data;
216 break;
217 case UART_LCRH:
218 lcrh = data;
219 break;
220 case UART_IFLS:
221 ifls = data;
222 break;
223 case UART_IMSC:
224 DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data);
225 setInterruptMask(data);
226 break;
227
228 case UART_ICR:
229 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
230 clearInterrupts(data);
231 if (device->dataAvailable()) {
232 DPRINTF(Uart, "Re-raising interrupt due to more data after "
233 "UART_ICR write\n");
234 dataAvailable();
235 }
236 break;
237 default:
238 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);
239 break;
240 }
241 pkt->makeAtomicResponse();
242 return pioDelay;
243}
244
245void
246Pl011::dataAvailable()
247{
248 /*@todo ignore the fifo, just say we have data now
249 * We might want to fix this, or we might not care */
250 DPRINTF(Uart, "Data available, scheduling interrupt\n");
251 raiseInterrupts(UART_RXINTR | UART_RTINTR);
252}
253
254void
255Pl011::generateInterrupt()
256{
257 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n",
258 imsc, rawInt, maskInt());
259
260 if (maskInt()) {
261 gic->sendInt(intNum);
262 DPRINTF(Uart, " -- Generated\n");
263 }
264}
265
266void
267Pl011::setInterrupts(uint16_t ints, uint16_t mask)
268{
269 const bool old_ints(!!maskInt());
270
271 imsc = mask;
272 rawInt = ints;
273
274 if (!old_ints && maskInt()) {
275 if (!intEvent.scheduled())
276 schedule(intEvent, curTick() + intDelay);
277 } else if (old_ints && !maskInt()) {
278 gic->clearInt(intNum);
279 }
280}
281
282
283
284void
285Pl011::serialize(CheckpointOut &cp) const
286{
287 DPRINTF(Checkpoint, "Serializing Arm PL011\n");
288 SERIALIZE_SCALAR(control);
289 SERIALIZE_SCALAR(fbrd);
290 SERIALIZE_SCALAR(ibrd);
291 SERIALIZE_SCALAR(lcrh);
292 SERIALIZE_SCALAR(ifls);
293
294 // Preserve backwards compatibility by giving these silly names.
295 paramOut(cp, "imsc_serial", imsc);
296 paramOut(cp, "rawInt_serial", rawInt);
297}
298
299void
300Pl011::unserialize(CheckpointIn &cp)
301{
302 DPRINTF(Checkpoint, "Unserializing Arm PL011\n");
303
304 UNSERIALIZE_SCALAR(control);
305 UNSERIALIZE_SCALAR(fbrd);
306 UNSERIALIZE_SCALAR(ibrd);
307 UNSERIALIZE_SCALAR(lcrh);
308 UNSERIALIZE_SCALAR(ifls);
309
310 // Preserve backwards compatibility by giving these silly names.
311 paramIn(cp, "imsc_serial", imsc);
312 paramIn(cp, "rawInt_serial", rawInt);
313}
314
315Pl011 *
316Pl011Params::create()
317{
318 return new Pl011(this);
319}
|