1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Chris Emmons
38 * Andreas Sandberg
39 */
40
41
42/** @file
43 * Implementiation of the ARM HDLcd controller.
44 *
45 * This implementation aims to have sufficient detail such that underrun
46 * conditions are reasonable / behave similar to reality. There are two
47 * 'engines' going at once. First, the DMA engine running at LCD clock
48 * frequency is responsible for filling the controller's internal buffer.
49 * The second engine runs at the pixel clock frequency and reads the pixels
50 * out of the internal buffer. The pixel rendering engine uses front / back
51 * porch and sync delays between lines and frames.
52 *
53 * If the pixel rendering engine does not have a pixel to display, it will
54 * cause an underrun event. The HDLcd controller, per spec, will stop
55 * issuing DMA requests for the rest of the frame and resume normal behavior
56 * on the subsequent frame. What pixels are rendered upon an underrun
57 * condition is different than the real hardware; while the user will see
58 * artifacts (previous frame mixed with current frame), it is not the same
59 * behavior as real hardware which repeats the last pixel value for the rest
60 * of the current frame. This compromise was made to save on memory and
61 * complexity and assumes that it is not important to accurately model the
62 * content of an underrun frame.
63 *
64 * KNOWN ISSUES
65 * <ul>
66 * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it
67 * doesn't have an AMBA ID as far as I know. That is the only
68 * bit of the AmbaDmaDevice interface that is irrelevant to it,
69 * so a fake AMBA ID is used for now. I didn't think inserting
70 * an extra layer of hierachy between AmbaDmaDevice and
71 * DmaDevice would be helpful to anyone else, but that may be
72 * the right answer.
73 * </ul>
74 */
75
76#ifndef __DEV_ARM_HDLCD_HH__
77#define __DEV_ARM_HDLCD_HH__
78
79#include <fstream>
80#include <memory>
81
82#include "base/bitmap.hh"
83#include "base/framebuffer.hh"
| 1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Chris Emmons
38 * Andreas Sandberg
39 */
40
41
42/** @file
43 * Implementiation of the ARM HDLcd controller.
44 *
45 * This implementation aims to have sufficient detail such that underrun
46 * conditions are reasonable / behave similar to reality. There are two
47 * 'engines' going at once. First, the DMA engine running at LCD clock
48 * frequency is responsible for filling the controller's internal buffer.
49 * The second engine runs at the pixel clock frequency and reads the pixels
50 * out of the internal buffer. The pixel rendering engine uses front / back
51 * porch and sync delays between lines and frames.
52 *
53 * If the pixel rendering engine does not have a pixel to display, it will
54 * cause an underrun event. The HDLcd controller, per spec, will stop
55 * issuing DMA requests for the rest of the frame and resume normal behavior
56 * on the subsequent frame. What pixels are rendered upon an underrun
57 * condition is different than the real hardware; while the user will see
58 * artifacts (previous frame mixed with current frame), it is not the same
59 * behavior as real hardware which repeats the last pixel value for the rest
60 * of the current frame. This compromise was made to save on memory and
61 * complexity and assumes that it is not important to accurately model the
62 * content of an underrun frame.
63 *
64 * KNOWN ISSUES
65 * <ul>
66 * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it
67 * doesn't have an AMBA ID as far as I know. That is the only
68 * bit of the AmbaDmaDevice interface that is irrelevant to it,
69 * so a fake AMBA ID is used for now. I didn't think inserting
70 * an extra layer of hierachy between AmbaDmaDevice and
71 * DmaDevice would be helpful to anyone else, but that may be
72 * the right answer.
73 * </ul>
74 */
75
76#ifndef __DEV_ARM_HDLCD_HH__
77#define __DEV_ARM_HDLCD_HH__
78
79#include <fstream>
80#include <memory>
81
82#include "base/bitmap.hh"
83#include "base/framebuffer.hh"
|
84#include "dev/arm/amba_device.hh"
85#include "dev/pixelpump.hh"
86#include "sim/serialize.hh"
87
88class VncInput;
89struct HDLcdParams;
90class HDLcdPixelPump;
91
92class HDLcd: public AmbaDmaDevice
93{
94 public:
95 HDLcd(const HDLcdParams *p);
96 ~HDLcd();
97
98 void regStats() override;
99
100 void serialize(CheckpointOut &cp) const override;
101 void unserialize(CheckpointIn &cp) override;
102
103 void drainResume() override;
104
105 public: // IO device interface
106 Tick read(PacketPtr pkt) override;
107 Tick write(PacketPtr pkt) override;
108
109 AddrRangeList getAddrRanges() const override { return addrRanges; }
110
111 protected: // Parameters
112 VncInput *vnc;
113 const bool workaroundSwapRB;
114 const bool workaroundDmaLineCount;
115 const AddrRangeList addrRanges;
116 const bool enableCapture;
117 const Addr pixelBufferSize;
118
119 protected: // Register handling
120 /** ARM HDLcd register offsets */
121 enum RegisterOffset {
122 Version = 0x0000,
123 Int_RawStat = 0x0010,
124 Int_Clear = 0x0014,
125 Int_Mask = 0x0018,
126 Int_Status = 0x001C,
127 Fb_Base = 0x0100,
128 Fb_Line_Length = 0x0104,
129 Fb_Line_Count = 0x0108,
130 Fb_Line_Pitch = 0x010C,
131 Bus_Options = 0x0110,
132 V_Sync = 0x0200,
133 V_Back_Porch = 0x0204,
134 V_Data = 0x0208,
135 V_Front_Porch = 0x020C,
136 H_Sync = 0x0210,
137 H_Back_Porch = 0x0214,
138 H_Data = 0x0218,
139 H_Front_Porch = 0x021C,
140 Polarities = 0x0220,
141 Command = 0x0230,
142 Pixel_Format = 0x0240,
143 Red_Select = 0x0244,
144 Green_Select = 0x0248,
145 Blue_Select = 0x024C,
146 };
147
148 /** Reset value for Bus_Options register */
149 static constexpr size_t BUS_OPTIONS_RESETV = 0x408;
150
151 /** Reset value for Version register */
152 static constexpr size_t VERSION_RESETV = 0x1CDC0000;
153
154 /** AXI port width in bytes */
155 static constexpr size_t AXI_PORT_WIDTH = 8;
156
157 /** max number of beats delivered in one dma burst */
158 static constexpr size_t MAX_BURST_LEN = 16;
159
160 /** Maximum number of bytes per pixel */
161 static constexpr size_t MAX_PIXEL_SIZE = 4;
162
163 /**
164 * @name RegisterFieldLayouts
165 * Bit layout declarations for multi-field registers.
166 */
167 /**@{*/
168 BitUnion32(VersionReg)
169 Bitfield<7,0> version_minor;
170 Bitfield<15,8> version_major;
171 Bitfield<31,16> product_id;
172 EndBitUnion(VersionReg)
173
174 static constexpr uint32_t INT_DMA_END = (1UL << 0);
175 static constexpr uint32_t INT_BUS_ERROR = (1UL << 1);
176 static constexpr uint32_t INT_VSYNC = (1UL << 2);
177 static constexpr uint32_t INT_UNDERRUN = (1UL << 3);
178
179 BitUnion32(FbLineCountReg)
180 Bitfield<11,0> fb_line_count;
181 Bitfield<31,12> reserved_31_12;
182 EndBitUnion(FbLineCountReg)
183
184 BitUnion32(BusOptsReg)
185 Bitfield<4,0> burst_len;
186 Bitfield<7,5> reserved_7_5;
187 Bitfield<11,8> max_outstanding;
188 Bitfield<31,12> reserved_31_12;
189 EndBitUnion(BusOptsReg)
190
191 BitUnion32(TimingReg)
192 Bitfield<11,0> val;
193 Bitfield<31,12> reserved_31_12;
194 EndBitUnion(TimingReg)
195
196 BitUnion32(PolaritiesReg)
197 Bitfield<0> vsync_polarity;
198 Bitfield<1> hsync_polarity;
199 Bitfield<2> dataen_polarity;
200 Bitfield<3> data_polarity;
201 Bitfield<4> pxlclk_polarity;
202 Bitfield<31,5> reserved_31_5;
203 EndBitUnion(PolaritiesReg)
204
205 BitUnion32(CommandReg)
206 Bitfield<0> enable;
207 Bitfield<31,1> reserved_31_1;
208 EndBitUnion(CommandReg)
209
210 BitUnion32(PixelFormatReg)
211 Bitfield<2,0> reserved_2_0;
212 Bitfield<4,3> bytes_per_pixel;
213 Bitfield<30,5> reserved_30_5;
214 Bitfield<31> big_endian;
215 EndBitUnion(PixelFormatReg)
216
217 BitUnion32(ColorSelectReg)
218 Bitfield<4,0> offset;
219 Bitfield<7,5> reserved_7_5;
220 Bitfield<11,8> size;
221 Bitfield<15,12> reserved_15_12;
222 Bitfield<23,16> default_color;
223 Bitfield<31,24> reserved_31_24;
224 EndBitUnion(ColorSelectReg)
225 /**@}*/
226
227 /**
228 * @name HDLCDRegisters
229 * HDLCD register contents.
230 */
231 /**@{*/
232 const VersionReg version; /**< Version register */
233 uint32_t int_rawstat; /**< Interrupt raw status register */
234 uint32_t int_mask; /**< Interrupt mask register */
235 uint32_t fb_base; /**< Frame buffer base address register */
236 uint32_t fb_line_length; /**< Frame buffer Line length register */
237 FbLineCountReg fb_line_count; /**< Frame buffer Line count register */
238 int32_t fb_line_pitch; /**< Frame buffer Line pitch register */
239 BusOptsReg bus_options; /**< Bus options register */
240 TimingReg v_sync; /**< Vertical sync width register */
241 TimingReg v_back_porch; /**< Vertical back porch width register */
242 TimingReg v_data; /**< Vertical data width register */
243 TimingReg v_front_porch; /**< Vertical front porch width register */
244 TimingReg h_sync; /**< Horizontal sync width register */
245 TimingReg h_back_porch; /**< Horizontal back porch width register */
246 TimingReg h_data; /**< Horizontal data width register */
247 TimingReg h_front_porch; /**< Horizontal front porch width reg */
248 PolaritiesReg polarities; /**< Polarities register */
249 CommandReg command; /**< Command register */
250 PixelFormatReg pixel_format; /**< Pixel format register */
251 ColorSelectReg red_select; /**< Red color select register */
252 ColorSelectReg green_select; /**< Green color select register */
253 ColorSelectReg blue_select; /**< Blue color select register */
254 /** @} */
255
256 uint32_t readReg(Addr offset);
257 void writeReg(Addr offset, uint32_t value);
258
259 PixelConverter pixelConverter() const;
260 DisplayTimings displayTimings() const;
261
262 void createDmaEngine();
263
264 void cmdEnable();
265 void cmdDisable();
266
267 bool enabled() const { return command.enable; }
268
269 public: // Pixel pump callbacks
270 bool pxlNext(Pixel &p);
271 void pxlVSyncBegin();
272 void pxlVSyncEnd();
273 void pxlUnderrun();
274 void pxlFrameDone();
275
276 protected: // Interrupt handling
277 /**
278 * Assign new interrupt values and update interrupt signals
279 *
280 * A new interrupt is scheduled signalled if the set of unmasked
281 * interrupts goes empty to non-empty. Conversely, if the set of
282 * unmasked interrupts goes from non-empty to empty, the interrupt
283 * signal is cleared.
284 *
285 * @param ints New <i>raw</i> interrupt status
286 * @param mask New interrupt mask
287 */
288 void setInterrupts(uint32_t ints, uint32_t mask);
289
290 /**
291 * Convenience function to update the interrupt mask
292 *
293 * @see setInterrupts
294 * @param mask New interrupt mask
295 */
296 void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); }
297
298 /**
299 * Convenience function to raise a new interrupt
300 *
301 * @see setInterrupts
302 * @param ints Set of interrupts to raise
303 */
304 void intRaise(uint32_t ints) {
305 setInterrupts(int_rawstat | ints, int_mask);
306 }
307
308 /**
309 * Convenience function to clear interrupts
310 *
311 * @see setInterrupts
312 * @param ints Set of interrupts to clear
313 */
314 void intClear(uint32_t ints) {
315 setInterrupts(int_rawstat & ~ints, int_mask);
316 }
317
318 /** Masked interrupt status register */
319 uint32_t intStatus() const { return int_rawstat & int_mask; }
320
321 protected: // Pixel output
322 class PixelPump : public BasePixelPump
323 {
324 public:
325 PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
326 : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {}
327
328 void dumpSettings();
329
330 protected:
331 bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
332
333 void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
334 void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
335
336 void onUnderrun(unsigned x, unsigned y) override {
337 parent.pxlUnderrun();
338 }
339
340 void onFrameDone() override { parent.pxlFrameDone(); }
341
342 protected:
343 HDLcd &parent;
344 };
345
346 /** Helper to write out bitmaps */
347 Bitmap bmp;
348
349 /** Picture of what the current frame buffer looks like */
| 85#include "dev/arm/amba_device.hh"
86#include "dev/pixelpump.hh"
87#include "sim/serialize.hh"
88
89class VncInput;
90struct HDLcdParams;
91class HDLcdPixelPump;
92
93class HDLcd: public AmbaDmaDevice
94{
95 public:
96 HDLcd(const HDLcdParams *p);
97 ~HDLcd();
98
99 void regStats() override;
100
101 void serialize(CheckpointOut &cp) const override;
102 void unserialize(CheckpointIn &cp) override;
103
104 void drainResume() override;
105
106 public: // IO device interface
107 Tick read(PacketPtr pkt) override;
108 Tick write(PacketPtr pkt) override;
109
110 AddrRangeList getAddrRanges() const override { return addrRanges; }
111
112 protected: // Parameters
113 VncInput *vnc;
114 const bool workaroundSwapRB;
115 const bool workaroundDmaLineCount;
116 const AddrRangeList addrRanges;
117 const bool enableCapture;
118 const Addr pixelBufferSize;
119
120 protected: // Register handling
121 /** ARM HDLcd register offsets */
122 enum RegisterOffset {
123 Version = 0x0000,
124 Int_RawStat = 0x0010,
125 Int_Clear = 0x0014,
126 Int_Mask = 0x0018,
127 Int_Status = 0x001C,
128 Fb_Base = 0x0100,
129 Fb_Line_Length = 0x0104,
130 Fb_Line_Count = 0x0108,
131 Fb_Line_Pitch = 0x010C,
132 Bus_Options = 0x0110,
133 V_Sync = 0x0200,
134 V_Back_Porch = 0x0204,
135 V_Data = 0x0208,
136 V_Front_Porch = 0x020C,
137 H_Sync = 0x0210,
138 H_Back_Porch = 0x0214,
139 H_Data = 0x0218,
140 H_Front_Porch = 0x021C,
141 Polarities = 0x0220,
142 Command = 0x0230,
143 Pixel_Format = 0x0240,
144 Red_Select = 0x0244,
145 Green_Select = 0x0248,
146 Blue_Select = 0x024C,
147 };
148
149 /** Reset value for Bus_Options register */
150 static constexpr size_t BUS_OPTIONS_RESETV = 0x408;
151
152 /** Reset value for Version register */
153 static constexpr size_t VERSION_RESETV = 0x1CDC0000;
154
155 /** AXI port width in bytes */
156 static constexpr size_t AXI_PORT_WIDTH = 8;
157
158 /** max number of beats delivered in one dma burst */
159 static constexpr size_t MAX_BURST_LEN = 16;
160
161 /** Maximum number of bytes per pixel */
162 static constexpr size_t MAX_PIXEL_SIZE = 4;
163
164 /**
165 * @name RegisterFieldLayouts
166 * Bit layout declarations for multi-field registers.
167 */
168 /**@{*/
169 BitUnion32(VersionReg)
170 Bitfield<7,0> version_minor;
171 Bitfield<15,8> version_major;
172 Bitfield<31,16> product_id;
173 EndBitUnion(VersionReg)
174
175 static constexpr uint32_t INT_DMA_END = (1UL << 0);
176 static constexpr uint32_t INT_BUS_ERROR = (1UL << 1);
177 static constexpr uint32_t INT_VSYNC = (1UL << 2);
178 static constexpr uint32_t INT_UNDERRUN = (1UL << 3);
179
180 BitUnion32(FbLineCountReg)
181 Bitfield<11,0> fb_line_count;
182 Bitfield<31,12> reserved_31_12;
183 EndBitUnion(FbLineCountReg)
184
185 BitUnion32(BusOptsReg)
186 Bitfield<4,0> burst_len;
187 Bitfield<7,5> reserved_7_5;
188 Bitfield<11,8> max_outstanding;
189 Bitfield<31,12> reserved_31_12;
190 EndBitUnion(BusOptsReg)
191
192 BitUnion32(TimingReg)
193 Bitfield<11,0> val;
194 Bitfield<31,12> reserved_31_12;
195 EndBitUnion(TimingReg)
196
197 BitUnion32(PolaritiesReg)
198 Bitfield<0> vsync_polarity;
199 Bitfield<1> hsync_polarity;
200 Bitfield<2> dataen_polarity;
201 Bitfield<3> data_polarity;
202 Bitfield<4> pxlclk_polarity;
203 Bitfield<31,5> reserved_31_5;
204 EndBitUnion(PolaritiesReg)
205
206 BitUnion32(CommandReg)
207 Bitfield<0> enable;
208 Bitfield<31,1> reserved_31_1;
209 EndBitUnion(CommandReg)
210
211 BitUnion32(PixelFormatReg)
212 Bitfield<2,0> reserved_2_0;
213 Bitfield<4,3> bytes_per_pixel;
214 Bitfield<30,5> reserved_30_5;
215 Bitfield<31> big_endian;
216 EndBitUnion(PixelFormatReg)
217
218 BitUnion32(ColorSelectReg)
219 Bitfield<4,0> offset;
220 Bitfield<7,5> reserved_7_5;
221 Bitfield<11,8> size;
222 Bitfield<15,12> reserved_15_12;
223 Bitfield<23,16> default_color;
224 Bitfield<31,24> reserved_31_24;
225 EndBitUnion(ColorSelectReg)
226 /**@}*/
227
228 /**
229 * @name HDLCDRegisters
230 * HDLCD register contents.
231 */
232 /**@{*/
233 const VersionReg version; /**< Version register */
234 uint32_t int_rawstat; /**< Interrupt raw status register */
235 uint32_t int_mask; /**< Interrupt mask register */
236 uint32_t fb_base; /**< Frame buffer base address register */
237 uint32_t fb_line_length; /**< Frame buffer Line length register */
238 FbLineCountReg fb_line_count; /**< Frame buffer Line count register */
239 int32_t fb_line_pitch; /**< Frame buffer Line pitch register */
240 BusOptsReg bus_options; /**< Bus options register */
241 TimingReg v_sync; /**< Vertical sync width register */
242 TimingReg v_back_porch; /**< Vertical back porch width register */
243 TimingReg v_data; /**< Vertical data width register */
244 TimingReg v_front_porch; /**< Vertical front porch width register */
245 TimingReg h_sync; /**< Horizontal sync width register */
246 TimingReg h_back_porch; /**< Horizontal back porch width register */
247 TimingReg h_data; /**< Horizontal data width register */
248 TimingReg h_front_porch; /**< Horizontal front porch width reg */
249 PolaritiesReg polarities; /**< Polarities register */
250 CommandReg command; /**< Command register */
251 PixelFormatReg pixel_format; /**< Pixel format register */
252 ColorSelectReg red_select; /**< Red color select register */
253 ColorSelectReg green_select; /**< Green color select register */
254 ColorSelectReg blue_select; /**< Blue color select register */
255 /** @} */
256
257 uint32_t readReg(Addr offset);
258 void writeReg(Addr offset, uint32_t value);
259
260 PixelConverter pixelConverter() const;
261 DisplayTimings displayTimings() const;
262
263 void createDmaEngine();
264
265 void cmdEnable();
266 void cmdDisable();
267
268 bool enabled() const { return command.enable; }
269
270 public: // Pixel pump callbacks
271 bool pxlNext(Pixel &p);
272 void pxlVSyncBegin();
273 void pxlVSyncEnd();
274 void pxlUnderrun();
275 void pxlFrameDone();
276
277 protected: // Interrupt handling
278 /**
279 * Assign new interrupt values and update interrupt signals
280 *
281 * A new interrupt is scheduled signalled if the set of unmasked
282 * interrupts goes empty to non-empty. Conversely, if the set of
283 * unmasked interrupts goes from non-empty to empty, the interrupt
284 * signal is cleared.
285 *
286 * @param ints New <i>raw</i> interrupt status
287 * @param mask New interrupt mask
288 */
289 void setInterrupts(uint32_t ints, uint32_t mask);
290
291 /**
292 * Convenience function to update the interrupt mask
293 *
294 * @see setInterrupts
295 * @param mask New interrupt mask
296 */
297 void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); }
298
299 /**
300 * Convenience function to raise a new interrupt
301 *
302 * @see setInterrupts
303 * @param ints Set of interrupts to raise
304 */
305 void intRaise(uint32_t ints) {
306 setInterrupts(int_rawstat | ints, int_mask);
307 }
308
309 /**
310 * Convenience function to clear interrupts
311 *
312 * @see setInterrupts
313 * @param ints Set of interrupts to clear
314 */
315 void intClear(uint32_t ints) {
316 setInterrupts(int_rawstat & ~ints, int_mask);
317 }
318
319 /** Masked interrupt status register */
320 uint32_t intStatus() const { return int_rawstat & int_mask; }
321
322 protected: // Pixel output
323 class PixelPump : public BasePixelPump
324 {
325 public:
326 PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk)
327 : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {}
328
329 void dumpSettings();
330
331 protected:
332 bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
333
334 void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
335 void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
336
337 void onUnderrun(unsigned x, unsigned y) override {
338 parent.pxlUnderrun();
339 }
340
341 void onFrameDone() override { parent.pxlFrameDone(); }
342
343 protected:
344 HDLcd &parent;
345 };
346
347 /** Helper to write out bitmaps */
348 Bitmap bmp;
349
350 /** Picture of what the current frame buffer looks like */
|