1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 105 unchanged lines hidden (view full) --- 114 GICR_IGRPMODR0 = SGI_base + 0x0d00, 115 // Non-secure Access Control Register 116 GICR_NSACR = SGI_base + 0x0e00, 117 }; 118 119 // Interrupt Priority Registers 120 static const AddrRange GICR_IPRIORITYR; 121 |
122 // GIC physical LPI Redistributor register 123 enum { 124 // Set LPI Pending Register 125 GICR_SETLPIR = RD_base + 0x0040, 126 // Clear LPI Pending Register 127 GICR_CLRLPIR = RD_base + 0x0048, 128 //Redistributor Properties Base Address Register 129 GICR_PROPBASER = RD_base + 0x0070, 130 // Redistributor LPI Pending Table Base Address Register 131 GICR_PENDBASER = RD_base + 0x0078, 132 // Redistributor Invalidate LPI Register 133 GICR_INVLPIR = RD_base + 0x00A0, 134 // Redistributor Invalidate All Register 135 GICR_INVALLR = RD_base + 0x00B0, 136 // Redistributor Synchronize Register 137 GICR_SYNCR = RD_base + 0x00C0, 138 }; 139 |
140 std::vector <uint8_t> irqGroup; 141 std::vector <bool> irqEnabled; 142 std::vector <bool> irqPending; 143 std::vector <bool> irqActive; 144 std::vector <uint8_t> irqPriority; 145 std::vector <Gicv3::IntTriggerType> irqConfig; 146 std::vector <uint8_t> irqGrpmod; 147 std::vector <uint8_t> irqNsacr; 148 149 bool DPG1S; 150 bool DPG1NS; 151 bool DPG0; |
152 bool EnableLPIs; |
153 |
154 Addr lpiConfigurationTablePtr; 155 uint8_t lpiIDBits; 156 Addr lpiPendingTablePtr; 157 158 BitUnion8(LPIConfigurationTableEntry) 159 Bitfield<7, 2> priority; 160 Bitfield<1> res1; 161 Bitfield<0> enable; 162 EndBitUnion(LPIConfigurationTableEntry) 163 164 std::vector<LPIConfigurationTableEntry> lpiConfigurationTable; 165 166 static const uint32_t GICR_CTLR_ENABLE_LPIS = 1 << 0; |
167 static const uint32_t GICR_CTLR_DPG0 = 1 << 24; 168 static const uint32_t GICR_CTLR_DPG1NS = 1 << 25; 169 static const uint32_t GICR_CTLR_DPG1S = 1 << 26; 170 171 public: 172 173 /* 174 * GICv3 defines only 2 64K consecutive frames for the redistributor 175 * (RD_base and SGI_base) but we are using 2 extra 64K stride frames 176 * to match GICv4 that defines 4 64K consecutive frames for them. 177 * Note this must match with DTB/DTS GIC node definition and boot 178 * loader code. 179 */ 180 static const uint32_t ADDR_RANGE_SIZE = 0x40000; 181 |
182 static const uint32_t SMALLEST_LPI_ID = 8192; 183 |
184 Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id); 185 ~Gicv3Redistributor(); 186 void init(); 187 void initState(); 188 189 uint64_t read(Addr addr, size_t size, bool is_secure_access); 190 void write(Addr addr, uint64_t data, size_t size, 191 bool is_secure_access); --- 5 unchanged lines hidden (view full) --- 197 198 Gicv3CPUInterface * 199 getCPUInterface() const 200 { 201 return cpuInterface; 202 } 203 204 bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group); |
205 void setClrLPI(uint64_t data, bool set); |
206 207 protected: 208 209 void reset(); 210 void update(); 211 void updateAndInformCPUInterface(); 212 Gicv3::IntStatus intStatus(uint32_t int_id); 213 Gicv3::GroupId getIntGroup(int int_id); 214 void activateIRQ(uint32_t int_id); 215 void deactivateIRQ(uint32_t int_id); |
216 void invalLpiConfig(uint32_t lpi_entry_index); |
217}; 218 219#endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__ |