gic_v3_redistributor.cc (14231:222f6512335e) gic_v3_redistributor.cc (14258:c75d22c32dec)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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52 SGI_base + 0x041f);
53
54Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
55 : gic(gic),
56 distributor(nullptr),
57 cpuInterface(nullptr),
58 cpuId(cpu_id),
59 memProxy(nullptr),
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 43 unchanged lines hidden (view full) ---

52 SGI_base + 0x041f);
53
54Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
55 : gic(gic),
56 distributor(nullptr),
57 cpuInterface(nullptr),
58 cpuId(cpu_id),
59 memProxy(nullptr),
60 irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
61 irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
62 irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
63 irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
64 irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
65 irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
66 irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
67 irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
60 peInLowPowerState(true),
61 irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
62 irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
63 irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
64 irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
65 irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
66 irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX, Gicv3::INT_EDGE_TRIGGERED),
67 irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
68 irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
69 DPG1S(false),
70 DPG1NS(false),
71 DPG0(false),
72 EnableLPIs(false),
73 lpiConfigurationTablePtr(0),
74 lpiIDBits(0),
75 lpiPendingTablePtr(0),
68 addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000)
69{
70}
71
72void
73Gicv3Redistributor::init()
74{
75 distributor = gic->getDistributor();
76 cpuInterface = gic->getCPUInterface(cpuId);
77
78 memProxy = &gic->getSystem()->physProxy;
79}
80
76 addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000)
77{
78}
79
80void
81Gicv3Redistributor::init()
82{
83 distributor = gic->getDistributor();
84 cpuInterface = gic->getCPUInterface(cpuId);
85
86 memProxy = &gic->getSystem()->physProxy;
87}
88
81void
82Gicv3Redistributor::initState()
83{
84 reset();
85}
86
87void
88Gicv3Redistributor::reset()
89{
90 peInLowPowerState = true;
91 std::fill(irqGroup.begin(), irqGroup.end(), 0);
92 std::fill(irqEnabled.begin(), irqEnabled.end(), false);
93 std::fill(irqPending.begin(), irqPending.end(), false);
94 std::fill(irqActive.begin(), irqActive.end(), false);
95 std::fill(irqPriority.begin(), irqPriority.end(), 0);
96
97 // SGIs have edge-triggered behavior
98 for (uint32_t int_id = 0; int_id < Gicv3::SGI_MAX; int_id++) {
99 irqConfig[int_id] = Gicv3::INT_EDGE_TRIGGERED;
100 }
101
102 std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0);
103 std::fill(irqNsacr.begin(), irqNsacr.end(), 0);
104 DPG1S = false;
105 DPG1NS = false;
106 DPG0 = false;
107 EnableLPIs = false;
108 lpiConfigurationTablePtr = 0;
109 lpiIDBits = 0;
110 lpiPendingTablePtr = 0;
111}
112
113uint64_t
114Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
115{
116 if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers
117 uint64_t value = 0;
118 int first_intid = addr - GICR_IPRIORITYR.start();
119
120 for (int i = 0, int_id = first_intid; i < size; i++, int_id++) {

--- 964 unchanged lines hidden --- 		89uint64_t
90Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
91{
92 if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers
93 uint64_t value = 0;
94 int first_intid = addr - GICR_IPRIORITYR.start();
95
96 for (int i = 0, int_id = first_intid; i < size; i++, int_id++) {

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