1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 */
30
31#include "dev/arm/gic_v3_redistributor.hh"
32
33#include "arch/arm/utility.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3_cpu_interface.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37
38const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
39 SGI_base + 0x041f);
40
41Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
42 : gic(gic),
43 distributor(nullptr),
44 cpuInterface(nullptr),

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86 irqConfig[int_id] = Gicv3::INT_EDGE_TRIGGERED;
87 }
88
89 std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0);
90 std::fill(irqNsacr.begin(), irqNsacr.end(), 0);
91 DPG1S = false;
92 DPG1NS = false;
93 DPG0 = false;
94}
95
96uint64_t
97Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
98{
99 if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers
100 uint64_t value = 0;
101 int first_intid = addr - GICR_IPRIORITYR.start();

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130 if (DPG1NS) {
131 value |= GICR_CTLR_DPG1NS;
132 }
133
134 if (DPG0) {
135 value |= GICR_CTLR_DPG0;
136 }
137
138 return value;
139 }
140
141 case GICR_IIDR: // Implementer Identification Register
142 //return 0x43b; // r0p0 GIC-500
143 return 0;
144
145 case GICR_TYPER: { // Type Register

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151 * LPI Configuration table)
152 * Processor_Number [23:8] == X
153 * (A unique identifier for the PE)
154 * DPGS [5] == 1
155 * (GICR_CTLR.DPG* bits are supported)
156 * Last [4] == X
157 * (This Redistributor is the highest-numbered Redistributor in
158 * a series of contiguous Redistributor pages)
159 * DirectLPI [3] == 0
160 * (direct injection of LPIs not supported)
161 * VLPIS [1] == 0
162 * (virtual LPIs not supported)
163 * PLPIS [0] == 0
164 * (physical LPIs not supported)
165 */
166 uint64_t affinity = getAffinity();
167 int last = cpuId == (gic->getSystem()->numContexts() - 1);
168 return (affinity << 32) | (1 << 24) | (cpuId << 8) |
169 (1 << 5) | (last << 4);
170 }
171
172 case GICR_WAKER: // Wake Register
173 if (!distributor->DS && !is_secure_access) {
174 // RAZ/WI for non-secure accesses
175 return 0;
176 }
177

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341 value |= irqNsacr[int_id] << i;
342 }
343 }
344 }
345
346 return value;
347 }
348
349 default:
350 panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
351 break;
352 }
353}
354
355void
356Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,

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377 "int_id %d priority %d\n", int_id, irqPriority[int_id]);
378 }
379
380 return;
381 }
382
383 switch (addr) {
384 case GICR_CTLR: {
385 // GICR_TYPER.LPIS is 0 so Enable_LPIs is RES0
386 DPG1S = data & GICR_CTLR_DPG1S;
387 DPG1NS = data & GICR_CTLR_DPG1NS;
388 DPG0 = data & GICR_CTLR_DPG0;
389 break;
390 }
391
392 case GICR_WAKER: // Wake Register
393 if (!distributor->DS && !is_secure_access) {

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601 irqNsacr[int_id] = (data >> i) & 0x3;
602 }
603 }
604 }
605
606 break;
607 }
608
609 default:
610 panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
611 break;
612 }
613}
614
615void
616Gicv3Redistributor::sendPPInt(uint32_t int_id)
617{
618 assert((int_id >= Gicv3::SGI_MAX) &&
619 (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
620 irqPending[int_id] = true;
621 DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): "
622 "int_id %d (PPI) pending bit set\n", int_id);
623 updateAndInformCPUInterface();

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699 cpuInterface->hppi.intid = int_id;
700 cpuInterface->hppi.prio = irqPriority[int_id];
701 cpuInterface->hppi.group = int_group;
702 new_hppi = true;
703 }
704 }
705 }
706
707 if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
708 cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
709 distributor->fullUpdate();
710 }
711}
712
713void
714Gicv3Redistributor::updateAndInformCPUInterface()
715{
716 update();
717 cpuInterface->update();
718}
719
720Gicv3::GroupId
721Gicv3Redistributor::getIntGroup(int int_id)

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809 SERIALIZE_CONTAINER(irqActive);
810 SERIALIZE_CONTAINER(irqPriority);
811 SERIALIZE_CONTAINER(irqConfig);
812 SERIALIZE_CONTAINER(irqGrpmod);
813 SERIALIZE_CONTAINER(irqNsacr);
814 SERIALIZE_SCALAR(DPG1S);
815 SERIALIZE_SCALAR(DPG1NS);
816 SERIALIZE_SCALAR(DPG0);
817}
818
819void
820Gicv3Redistributor::unserialize(CheckpointIn & cp)
821{
822 UNSERIALIZE_SCALAR(peInLowPowerState);
823 UNSERIALIZE_CONTAINER(irqGroup);
824 UNSERIALIZE_CONTAINER(irqEnabled);
825 UNSERIALIZE_CONTAINER(irqPending);
826 UNSERIALIZE_CONTAINER(irqActive);
827 UNSERIALIZE_CONTAINER(irqPriority);
828 UNSERIALIZE_CONTAINER(irqConfig);
829 UNSERIALIZE_CONTAINER(irqGrpmod);
830 UNSERIALIZE_CONTAINER(irqNsacr);
831 UNSERIALIZE_SCALAR(DPG1S);
832 UNSERIALIZE_SCALAR(DPG1NS);
833 UNSERIALIZE_SCALAR(DPG0);
834}