| gic_v3_distributor.cc (13531:e6f1bf55d038) | gic_v3_distributor.cc (13690:284050bbec68) |
|---|---|
| 1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 437 unchanged lines hidden (view full) --- 446 * (1 of N SPI interrupts are not supported) 447 * A3V [24] == 1 448 * (Supports nonzero values of Affinity level 3) 449 * IDbits [23:19] == 0xf 450 * (The number of interrupt identifier bits supported, minus one) 451 * DVIS [18] == 0 452 * (The implementation does not support Direct Virtual LPI 453 * injection) | 1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 437 unchanged lines hidden (view full) --- 446 * (1 of N SPI interrupts are not supported) 447 * A3V [24] == 1 448 * (Supports nonzero values of Affinity level 3) 449 * IDbits [23:19] == 0xf 450 * (The number of interrupt identifier bits supported, minus one) 451 * DVIS [18] == 0 452 * (The implementation does not support Direct Virtual LPI 453 * injection) |
| 454 * LPIS [17] == 0 | 454 * LPIS [17] == 1 |
| 455 * (The implementation does not support LPIs) 456 * MBIS [16] == 0 457 * (The implementation does not support message-based interrupts 458 * by writing to Distributor registers) 459 * SecurityExtn [10] == X 460 * (The GIC implementation supports two Security states) 461 * CPUNumber [7:5] == 0 462 * (since for us ARE is always 1 [(ARE = 0) == Gicv2 legacy]) 463 * ITLinesNumber [4:0] == N 464 * (MaxSPIIntId = 32 (N + 1) - 1) 465 */ 466 { 467 int max_spi_int_id = itLines - 1; 468 int it_lines_number = ceil((max_spi_int_id + 1) / 32.0) - 1; 469 return (1 << 26) | (1 << 25) | (1 << 24) | (0xf << 19) | | 455 * (The implementation does not support LPIs) 456 * MBIS [16] == 0 457 * (The implementation does not support message-based interrupts 458 * by writing to Distributor registers) 459 * SecurityExtn [10] == X 460 * (The GIC implementation supports two Security states) 461 * CPUNumber [7:5] == 0 462 * (since for us ARE is always 1 [(ARE = 0) == Gicv2 legacy]) 463 * ITLinesNumber [4:0] == N 464 * (MaxSPIIntId = 32 (N + 1) - 1) 465 */ 466 { 467 int max_spi_int_id = itLines - 1; 468 int it_lines_number = ceil((max_spi_int_id + 1) / 32.0) - 1; 469 return (1 << 26) | (1 << 25) | (1 << 24) | (0xf << 19) | |
| 470 (gic->getSystem()->haveSecurity() << 10) | | 470 (1 << 17) | (gic->getSystem()->haveSecurity() << 10) | |
| 471 (it_lines_number << 0); 472 } 473 474 case GICD_IIDR: // Implementer Identification Register 475 //return 0x43b; // ARM JEP106 code (r0p0 GIC-500) 476 return 0; 477 478 case GICD_STATUSR: // Error Reporting Status Register --- 654 unchanged lines hidden --- | 471 (it_lines_number << 0); 472 } 473 474 case GICD_IIDR: // Implementer Identification Register 475 //return 0x43b; // ARM JEP106 code (r0p0 GIC-500) 476 return 0; 477 478 case GICD_STATUSR: // Error Reporting Status Register --- 654 unchanged lines hidden --- |