1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0eff);
65const AddrRange Gicv3Distributor::GICD_CPENDSGIR (0x0f10, 0x0f1f);
66const AddrRange Gicv3Distributor::GICD_SPENDSGIR (0x0f20, 0x0f2f);
67const AddrRange Gicv3Distributor::GICD_IROUTER (0x6000, 0x7fe0);
68
69Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)
70 : gic(gic),
71 itLines(it_lines),
72 irqGroup(it_lines),
73 irqEnabled(it_lines),
74 irqPending(it_lines),
75 irqActive(it_lines),
76 irqPriority(it_lines),
77 irqConfig(it_lines),
78 irqGrpmod(it_lines),
79 irqNsacr(it_lines),
80 irqAffinityRouting(it_lines),
81 gicdTyper(0),
82 gicdPidr0(0x92),
83 gicdPidr1(0xb4),
84 gicdPidr2(0x3b),
85 gicdPidr3(0),
86 gicdPidr4(0x44)
87{
88 panic_if(it_lines > Gicv3::INTID_SECURE, "Invalid value for it_lines!");

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112 * (MaxSPIIntId = 32 (N + 1) - 1)
113 */
114 int max_spi_int_id = itLines - 1;
115 int it_lines_number = divCeil(max_spi_int_id + 1, 32) - 1;
116 gicdTyper = (1 << 26) | (1 << 25) | (1 << 24) | (IDBITS << 19) |
117 (1 << 17) | (1 << 16) |
118 ((gic->getSystem()->haveSecurity() ? 1 : 0) << 10) |
119 (it_lines_number << 0);
120}
121
122void
123Gicv3Distributor::init()
124{
125}
126
127void
128Gicv3Distributor::initState()
129{
130 reset();
131}
132
133void
134Gicv3Distributor::reset()
135{
136 std::fill(irqGroup.begin(), irqGroup.end(), 0);
137 // Imp. defined reset value
138 std::fill(irqEnabled.begin(), irqEnabled.end(), false);
139 std::fill(irqPending.begin(), irqPending.end(), false);
140 std::fill(irqActive.begin(), irqActive.end(), false);
141 // Imp. defined reset value
142 std::fill(irqPriority.begin(), irqPriority.end(), 0xAAAAAAAA);
143 std::fill(irqConfig.begin(), irqConfig.end(),
144 Gicv3::INT_LEVEL_SENSITIVE); // Imp. defined reset value
145 std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0);
146 std::fill(irqNsacr.begin(), irqNsacr.end(), 0);
147 /*
148 * For our implementation affinity routing is always enabled,
149 * no GICv2 legacy
150 */
151 ARE = true;
152
153 if (gic->getSystem()->haveSecurity()) {
154 DS = false;
155 } else {
156 DS = true;
157 }
158
159 EnableGrp0 = 0;
160 EnableGrp1NS = 0;
161 EnableGrp1S = 0;
162}
163
164uint64_t
165Gicv3Distributor::read(Addr addr, size_t size, bool is_secure_access)
166{
167 if (GICD_IGROUPR.contains(addr)) { // Interrupt Group Registers
168 uint64_t val = 0x0;
169

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