1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0eff);
65const AddrRange Gicv3Distributor::GICD_CPENDSGIR (0x0f10, 0x0f1f);
66const AddrRange Gicv3Distributor::GICD_SPENDSGIR (0x0f20, 0x0f2f);
67const AddrRange Gicv3Distributor::GICD_IROUTER (0x6000, 0x7fe0);
68
69Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)
70 : gic(gic),
71 itLines(it_lines),
72 ARE(true),
73 EnableGrp1S(0),
74 EnableGrp1NS(0),
75 EnableGrp0(0),
76 irqGroup(it_lines, 0),
77 irqEnabled(it_lines, false),
78 irqPending(it_lines, false),
79 irqActive(it_lines, false),
80 irqPriority(it_lines, 0xAA),
81 irqConfig(it_lines, Gicv3::INT_LEVEL_SENSITIVE),
82 irqGrpmod(it_lines, 0),
83 irqNsacr(it_lines, 0),
84 irqAffinityRouting(it_lines, 0),
85 gicdTyper(0),
86 gicdPidr0(0x92),
87 gicdPidr1(0xb4),
88 gicdPidr2(0x3b),
89 gicdPidr3(0),
90 gicdPidr4(0x44)
91{
92 panic_if(it_lines > Gicv3::INTID_SECURE, "Invalid value for it_lines!");

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116 * (MaxSPIIntId = 32 (N + 1) - 1)
117 */
118 int max_spi_int_id = itLines - 1;
119 int it_lines_number = divCeil(max_spi_int_id + 1, 32) - 1;
120 gicdTyper = (1 << 26) | (1 << 25) | (1 << 24) | (IDBITS << 19) |
121 (1 << 17) | (1 << 16) |
122 ((gic->getSystem()->haveSecurity() ? 1 : 0) << 10) |
123 (it_lines_number << 0);
124
125 if (gic->getSystem()->haveSecurity()) {
126 DS = false;
127 } else {
128 DS = true;
129 }
130}
131
132void
133Gicv3Distributor::init()
134{
135}
136
137uint64_t
138Gicv3Distributor::read(Addr addr, size_t size, bool is_secure_access)
139{
140 if (GICD_IGROUPR.contains(addr)) { // Interrupt Group Registers
141 uint64_t val = 0x0;
142

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