gic_v3_cpu_interface.hh (14237:fa3f5209a8e8) gic_v3_cpu_interface.hh (14243:6116e1413f80)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 324 unchanged lines hidden (view full) ---

333 int virtualFindActive(uint32_t intid) const;
334 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
335 uint8_t virtualHighestActivePriority() const;
336 void virtualIncrementEOICount();
337 bool virtualIsEOISplitMode() const;
338 void virtualUpdate();
339 RegVal bpr1(Gicv3::GroupId group);
340
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 324 unchanged lines hidden (view full) ---

333 int virtualFindActive(uint32_t intid) const;
334 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
335 uint8_t virtualHighestActivePriority() const;
336 void virtualIncrementEOICount();
337 bool virtualIsEOISplitMode() const;
338 void virtualUpdate();
339 RegVal bpr1(Gicv3::GroupId group);
340
341 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
342 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
341 public:
342
343 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
344
345 void init();
346 void initState();
347
348 public: // BaseISADevice
349 RegVal readMiscReg(int misc_reg) override;
350 void setMiscReg(int misc_reg, RegVal val) override;
351 void setThreadContext(ThreadContext *tc) override;
352};
353
354#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
343 public:
344
345 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
346
347 void init();
348 void initState();
349
350 public: // BaseISADevice
351 RegVal readMiscReg(int misc_reg) override;
352 void setMiscReg(int misc_reg, RegVal val) override;
353 void setThreadContext(ThreadContext *tc) override;
354};
355
356#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__