gic_v3_cpu_interface.hh (13760:fcec3c5abbdf) gic_v3_cpu_interface.hh (13826:34a9929c35eb)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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46
47 protected:
48
49 Gicv3 * gic;
50 Gicv3Redistributor * redistributor;
51 Gicv3Distributor * distributor;
52 uint32_t cpuId;
53
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 37 unchanged lines hidden (view full) ---

46
47 protected:
48
49 Gicv3 * gic;
50 Gicv3Redistributor * redistributor;
51 Gicv3Distributor * distributor;
52 uint32_t cpuId;
53
54 ArmInterruptPin *maintenanceInterrupt;
55
54 BitUnion64(ICC_CTLR_EL1)
55 Bitfield<63, 20> res0_3;
56 Bitfield<19> ExtRange;
57 Bitfield<18> RSS;
58 Bitfield<17, 16> res0_2;
59 Bitfield<15> A3V;
60 Bitfield<14> SEIS;
61 Bitfield<13, 11> IDbits;

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302 bool hppviCanPreempt(int lrIdx) const;
303 bool inSecureState() const;
304 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
305 bool isAA64() const;
306 bool isEL3OrMon() const;
307 bool isEOISplitMode() const;
308 bool isSecureBelowEL3() const;
309 ICH_MISR_EL2 maintenanceInterruptStatus() const;
56 BitUnion64(ICC_CTLR_EL1)
57 Bitfield<63, 20> res0_3;
58 Bitfield<19> ExtRange;
59 Bitfield<18> RSS;
60 Bitfield<17, 16> res0_2;
61 Bitfield<15> A3V;
62 Bitfield<14> SEIS;
63 Bitfield<13, 11> IDbits;

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304 bool hppviCanPreempt(int lrIdx) const;
305 bool inSecureState() const;
306 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
307 bool isAA64() const;
308 bool isEL3OrMon() const;
309 bool isEOISplitMode() const;
310 bool isSecureBelowEL3() const;
311 ICH_MISR_EL2 maintenanceInterruptStatus() const;
310 RegVal readMiscReg(int misc_reg) override;
311 void reset();
312 void serialize(CheckpointOut & cp) const override;
312 void reset();
313 void serialize(CheckpointOut & cp) const override;
313 void setMiscReg(int misc_reg, RegVal val) override;
314 void unserialize(CheckpointIn & cp) override;
315 void update();
316 void virtualActivateIRQ(uint32_t lrIdx);
317 void virtualDeactivateIRQ(int lrIdx);
318 uint8_t virtualDropPriority();
319 int virtualFindActive(uint32_t intid) const;
320 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
321 uint8_t virtualHighestActivePriority() const;
322 void virtualIncrementEOICount();
323 bool virtualIsEOISplitMode() const;
324 void virtualUpdate();
325
326 public:
327
328 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
329
330 void init();
331 void initState();
314 void unserialize(CheckpointIn & cp) override;
315 void update();
316 void virtualActivateIRQ(uint32_t lrIdx);
317 void virtualDeactivateIRQ(int lrIdx);
318 uint8_t virtualDropPriority();
319 int virtualFindActive(uint32_t intid) const;
320 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
321 uint8_t virtualHighestActivePriority() const;
322 void virtualIncrementEOICount();
323 bool virtualIsEOISplitMode() const;
324 void virtualUpdate();
325
326 public:
327
328 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
329
330 void init();
331 void initState();
332
333 public: // BaseISADevice
334 RegVal readMiscReg(int misc_reg) override;
335 void setMiscReg(int misc_reg, RegVal val) override;
336 void setThreadContext(ThreadContext *tc) override;
332};
333
334#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
337};
338
339#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__