gic_v3_cpu_interface.hh (13580:18ed3315bdb6) | gic_v3_cpu_interface.hh (13760:fcec3c5abbdf) |
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1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__ 32#define __DEV_ARM_GICV3_CPU_INTERFACE_H__ 33 34#include "arch/arm/isa_device.hh" 35#include "dev/arm/gic_v3.hh" 36 | 1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__ 32#define __DEV_ARM_GICV3_CPU_INTERFACE_H__ 33 34#include "arch/arm/isa_device.hh" 35#include "dev/arm/gic_v3.hh" 36 |
37class Gicv3Redistributor; | |
38class Gicv3Distributor; | 37class Gicv3Distributor; |
38class Gicv3Redistributor; |
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39 40class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable 41{ 42 private: 43 | 39 40class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable 41{ 42 private: 43 |
44 friend class Gicv3Redistributor; | |
45 friend class Gicv3Distributor; | 44 friend class Gicv3Distributor; |
45 friend class Gicv3Redistributor; |
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46 47 protected: 48 49 Gicv3 * gic; 50 Gicv3Redistributor * redistributor; 51 Gicv3Distributor * distributor; 52 uint32_t cpuId; 53 | 46 47 protected: 48 49 Gicv3 * gic; 50 Gicv3Redistributor * redistributor; 51 Gicv3Distributor * distributor; 52 uint32_t cpuId; 53 |
54 static const uint32_t ICC_SRE_EL1_SRE = 1 << 0; 55 static const uint32_t ICC_SRE_EL1_DFB = 1 << 1; 56 static const uint32_t ICC_SRE_EL1_DIB = 1 << 2; | 54 BitUnion64(ICC_CTLR_EL1) 55 Bitfield<63, 20> res0_3; 56 Bitfield<19> ExtRange; 57 Bitfield<18> RSS; 58 Bitfield<17, 16> res0_2; 59 Bitfield<15> A3V; 60 Bitfield<14> SEIS; 61 Bitfield<13, 11> IDbits; 62 Bitfield<10, 8> PRIbits; 63 Bitfield<7> res0_1; 64 Bitfield<6> PMHE; 65 Bitfield<5, 2> res0_0; 66 Bitfield<1> EOImode; 67 Bitfield<0> CBPR; 68 EndBitUnion(ICC_CTLR_EL1) |
57 | 69 |
58 static const uint32_t ICC_SRE_EL2_SRE = 1 << 0; 59 static const uint32_t ICC_SRE_EL2_DFB = 1 << 1; 60 static const uint32_t ICC_SRE_EL2_DIB = 1 << 2; 61 static const uint32_t ICC_SRE_EL2_ENABLE = 1 << 3; | 70 BitUnion64(ICC_CTLR_EL3) 71 Bitfield<63, 20> res0_2; 72 Bitfield<19> ExtRange; 73 Bitfield<18> RSS; 74 Bitfield<17> nDS; 75 Bitfield<16> res0_1; 76 Bitfield<15> A3V; 77 Bitfield<14> SEIS; 78 Bitfield<13, 11> IDbits; 79 Bitfield<10, 8> PRIbits; 80 Bitfield<7> res0_0; 81 Bitfield<6> PMHE; 82 Bitfield<5> RM; 83 Bitfield<4> EOImode_EL1NS; 84 Bitfield<3> EOImode_EL1S; 85 Bitfield<2> EOImode_EL3; 86 Bitfield<1> CBPR_EL1NS; 87 Bitfield<0> CBPR_EL1S; 88 EndBitUnion(ICC_CTLR_EL3) |
62 | 89 |
63 static const uint32_t ICC_SRE_EL3_SRE = 1 << 0; 64 static const uint32_t ICC_SRE_EL3_DFB = 1 << 1; 65 static const uint32_t ICC_SRE_EL3_DIB = 1 << 2; 66 static const uint32_t ICC_SRE_EL3_ENABLE = 1 << 3; | 90 BitUnion64(ICC_IGRPEN0_EL1) 91 Bitfield<63, 1> res0; 92 Bitfield<0> Enable; 93 EndBitUnion(ICC_IGRPEN0_EL1) |
67 | 94 |
68 static const uint32_t ICC_CTLR_EL3_CBPR_EL1S = 1 << 0; 69 static const uint32_t ICC_CTLR_EL3_CBPR_EL1NS = 1 << 1; 70 static const uint32_t ICC_CTLR_EL3_EOIMODE_EL3 = 1 << 2; 71 static const uint32_t ICC_CTLR_EL3_EOIMODE_EL1S = 1 << 3; 72 static const uint32_t ICC_CTLR_EL3_EOIMODE_EL1NS = 1 << 4; 73 static const uint32_t ICC_CTLR_EL3_RM = 1 << 5; 74 static const uint32_t ICC_CTLR_EL3_PMHE = 1 << 6; 75 static const uint32_t ICC_CTLR_EL3_PRIBITS_SHIFT = 8; 76 static const uint32_t ICC_CTLR_EL3_IDBITS_SHIFT = 11; 77 static const uint32_t ICC_CTLR_EL3_SEIS = 1 << 14; 78 static const uint32_t ICC_CTLR_EL3_A3V = 1 << 15; 79 static const uint32_t ICC_CTLR_EL3_nDS = 1 << 17; 80 static const uint32_t ICC_CTLR_EL3_RSS = 1 << 18; | 95 BitUnion64(ICC_IGRPEN1_EL1) 96 Bitfield<63, 1> res0; 97 Bitfield<0> Enable; 98 EndBitUnion(ICC_IGRPEN1_EL1) |
81 | 99 |
82 static const uint32_t ICC_CTLR_EL1_CBPR = 1 << 0; 83 static const uint32_t ICC_CTLR_EL1_EOIMODE = 1 << 1; 84 static const uint32_t ICC_CTLR_EL1_PMHE = 1 << 6; 85 static const uint32_t ICC_CTLR_EL1_SEIS = 1 << 14; 86 static const uint32_t ICC_CTLR_EL1_A3V = 1 << 15; 87 static const uint32_t ICC_CTLR_EL1_RSS = 1 << 18; 88 static const uint32_t ICC_CTLR_EL1_PRIBITS_SHIFT = 8; 89 static const uint32_t ICC_CTLR_EL1_PRIBITS_MASK = 90 7U << ICC_CTLR_EL1_PRIBITS_SHIFT; 91 static const uint32_t ICC_CTLR_EL1_IDBITS_SHIFT = 11; | 100 BitUnion64(ICC_IGRPEN1_EL3) 101 Bitfield<63, 2> res0; 102 Bitfield<1> EnableGrp1S; 103 Bitfield<0> EnableGrp1NS; 104 EndBitUnion(ICC_IGRPEN1_EL3) |
92 | 105 |
93 static const uint32_t ICC_IGRPEN0_EL1_ENABLE = 1 << 0; 94 static const uint32_t ICC_IGRPEN1_EL1_ENABLE = 1 << 0; | 106 BitUnion64(ICC_SRE_EL1) 107 Bitfield<63, 3> res0; 108 Bitfield<2> DIB; 109 Bitfield<1> DFB; 110 Bitfield<0> SRE; 111 EndBitUnion(ICC_SRE_EL1) |
95 | 112 |
96 static const uint32_t ICC_IGRPEN1_EL3_ENABLEGRP1NS = 1 << 0; 97 static const uint32_t ICC_IGRPEN1_EL3_ENABLEGRP1S = 1 << 1; | 113 BitUnion64(ICC_SRE_EL2) 114 Bitfield<63, 4> res0; 115 Bitfield<3> Enable; 116 Bitfield<2> DIB; 117 Bitfield<1> DFB; 118 Bitfield<0> SRE; 119 EndBitUnion(ICC_SRE_EL2) |
98 | 120 |
121 BitUnion64(ICC_SRE_EL3) 122 Bitfield<63, 4> res0; 123 Bitfield<3> Enable; 124 Bitfield<2> DIB; 125 Bitfield<1> DFB; 126 Bitfield<0> SRE; 127 EndBitUnion(ICC_SRE_EL3) 128 |
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99 static const uint8_t PRIORITY_BITS = 5; 100 | 129 static const uint8_t PRIORITY_BITS = 5; 130 |
101 /* Minimum BPR for Secure, or when security not enabled */ | 131 // Minimum BPR for Secure, or when security not enabled |
102 static const uint8_t GIC_MIN_BPR = 2; | 132 static const uint8_t GIC_MIN_BPR = 2; |
103 /* Minimum BPR for Nonsecure when security is enabled */ | 133 // Minimum BPR for Nonsecure when security is enabled |
104 static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1; 105 | 134 static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1; 135 |
106 static const uint8_t VIRTUAL_PRIORITY_BITS = 5; | 136 static const uint8_t VIRTUAL_PRIORITY_BITS = 5; |
107 static const uint8_t VIRTUAL_PREEMPTION_BITS = 5; | 137 static const uint8_t VIRTUAL_PREEMPTION_BITS = 5; |
108 static const uint8_t VIRTUAL_NUM_LIST_REGS = 16; | 138 static const uint8_t VIRTUAL_NUM_LIST_REGS = 16; |
109 110 static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS; 111 112 typedef struct { 113 uint32_t intid; 114 uint8_t prio; 115 Gicv3::GroupId group; 116 } hppi_t; 117 118 hppi_t hppi; 119 120 // GIC CPU interface memory mapped control registers (legacy) 121 enum { | 139 140 static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS; 141 142 typedef struct { 143 uint32_t intid; 144 uint8_t prio; 145 Gicv3::GroupId group; 146 } hppi_t; 147 148 hppi_t hppi; 149 150 // GIC CPU interface memory mapped control registers (legacy) 151 enum { |
122 GICC_CTLR = 0x0000, 123 GICC_PMR = 0x0004, 124 GICC_BPR = 0x0008, 125 GICC_IAR = 0x000C, 126 GICC_EOIR = 0x0010, 127 GICC_RPR = 0x0014, 128 GICC_HPPI = 0x0018, 129 GICC_ABPR = 0x001C, 130 GICC_AIAR = 0x0020, 131 GICC_AEOIR = 0x0024, 132 GICC_AHPPIR = 0x0028, | 152 GICC_CTLR = 0x0000, 153 GICC_PMR = 0x0004, 154 GICC_BPR = 0x0008, 155 GICC_IAR = 0x000C, 156 GICC_EOIR = 0x0010, 157 GICC_RPR = 0x0014, 158 GICC_HPPI = 0x0018, 159 GICC_ABPR = 0x001C, 160 GICC_AIAR = 0x0020, 161 GICC_AEOIR = 0x0024, 162 GICC_AHPPIR = 0x0028, |
133 GICC_STATUSR = 0x002C, | 163 GICC_STATUSR = 0x002C, |
134 GICC_IIDR = 0x00FC, | 164 GICC_IIDR = 0x00FC, |
135 }; 136 137 static const AddrRange GICC_APR; 138 static const AddrRange GICC_NSAPR; 139 140 // GIC CPU virtual interface memory mapped control registers (legacy) 141 enum { | 165 }; 166 167 static const AddrRange GICC_APR; 168 static const AddrRange GICC_NSAPR; 169 170 // GIC CPU virtual interface memory mapped control registers (legacy) 171 enum { |
142 GICH_HCR = 0x0000, 143 GICH_VTR = 0x0004, 144 GICH_VMCR = 0x0008, 145 GICH_MISR = 0x0010, 146 GICH_EISR = 0x0020, | 172 GICH_HCR = 0x0000, 173 GICH_VTR = 0x0004, 174 GICH_VMCR = 0x0008, 175 GICH_MISR = 0x0010, 176 GICH_EISR = 0x0020, |
147 GICH_ELRSR = 0x0030, 148 }; 149 150 static const AddrRange GICH_APR; 151 static const AddrRange GICH_LR; 152 | 177 GICH_ELRSR = 0x0030, 178 }; 179 180 static const AddrRange GICH_APR; 181 static const AddrRange GICH_LR; 182 |
153 static const uint32_t ICH_HCR_EL2_EN = 1 << 0; 154 static const uint32_t ICH_HCR_EL2_UIE = 1 << 1; 155 static const uint32_t ICH_HCR_EL2_LRENPIE = 1 << 2; 156 static const uint32_t ICH_HCR_EL2_NPIE = 1 << 3; 157 static const uint32_t ICH_HCR_EL2_VGRP0EIE = 1 << 4; 158 static const uint32_t ICH_HCR_EL2_VGRP0DIE = 1 << 5; 159 static const uint32_t ICH_HCR_EL2_VGRP1EIE = 1 << 6; 160 static const uint32_t ICH_HCR_EL2_VGRP1DIE = 1 << 7; 161 static const uint32_t ICH_HCR_EL2_TC = 1 << 10; 162 static const uint32_t ICH_HCR_EL2_TALL0 = 1 << 11; 163 static const uint32_t ICH_HCR_EL2_TALL1 = 1 << 12; 164 static const uint32_t ICH_HCR_EL2_TSEI = 1 << 13; 165 static const uint32_t ICH_HCR_EL2_TDIR = 1 << 14; 166 static const uint32_t ICH_HCR_EL2_EOICOUNT_MASK = 0x1fU << 27; | 183 BitUnion64(ICH_HCR_EL2) 184 Bitfield<63, 32> res0_2; 185 Bitfield<31, 27> EOIcount; 186 Bitfield<26, 15> res0_1; 187 Bitfield<14> TDIR; 188 Bitfield<13> TSEI; 189 Bitfield<12> TALL1; 190 Bitfield<11> TALL0; 191 Bitfield<10> TC; 192 Bitfield<9, 8> res0_0; 193 Bitfield<7> VGrp1DIE; 194 Bitfield<6> VGrp1EIE; 195 Bitfield<5> VGrp0DIE; 196 Bitfield<4> VGrp0EIE; 197 Bitfield<3> NPIE; 198 Bitfield<2> LRENPIE; 199 Bitfield<1> UIE; 200 Bitfield<0> En; 201 EndBitUnion(ICH_HCR_EL2) |
167 | 202 |
168 static const uint64_t ICH_LR_EL2_VINTID_SHIFT = 0; 169 static const uint64_t ICH_LR_EL2_VINTID_LENGTH = 32; 170 static const uint64_t ICH_LR_EL2_VINTID_MASK = 171 (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT); 172 static const uint64_t ICH_LR_EL2_PINTID_SHIFT = 32; 173 static const uint64_t ICH_LR_EL2_PINTID_LENGTH = 10; 174 static const uint64_t ICH_LR_EL2_PINTID_MASK = 175 (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT); 176 /* Note that EOI shares with the top bit of the pINTID field */ 177 static const uint64_t ICH_LR_EL2_EOI = (1ULL << 41); 178 static const uint64_t ICH_LR_EL2_PRIORITY_SHIFT = 48; 179 static const uint64_t ICH_LR_EL2_PRIORITY_LENGTH = 8; 180 static const uint64_t ICH_LR_EL2_PRIORITY_MASK = 181 (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT); 182 static const uint64_t ICH_LR_EL2_GROUP = (1ULL << 60); 183 static const uint64_t ICH_LR_EL2_HW = (1ULL << 61); 184 static const uint64_t ICH_LR_EL2_STATE_SHIFT = 62; 185 static const uint64_t ICH_LR_EL2_STATE_LENGTH = 2; 186 static const uint64_t ICH_LR_EL2_STATE_MASK = 187 (3ULL << ICH_LR_EL2_STATE_SHIFT); 188 /* values for the state field: */ 189 static const uint64_t ICH_LR_EL2_STATE_INVALID = 0; 190 static const uint64_t ICH_LR_EL2_STATE_PENDING = 1; 191 static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2; | 203 BitUnion64(ICH_LR_EL2) 204 Bitfield<63, 62> State; 205 Bitfield<61> HW; 206 Bitfield<60> Group; 207 Bitfield<59, 56> res0_1; 208 Bitfield<55, 48> Priority; 209 Bitfield<47, 45> res0_0; 210 Bitfield<44, 32> pINTID; 211 Bitfield<41> EOI; 212 Bitfield<31, 0> vINTID; 213 EndBitUnion(ICH_LR_EL2) 214 215 static const uint64_t ICH_LR_EL2_STATE_INVALID = 0; 216 static const uint64_t ICH_LR_EL2_STATE_PENDING = 1; 217 static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2; |
192 static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3; | 218 static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3; |
193 static const uint64_t ICH_LR_EL2_STATE_PENDING_BIT = 194 (1ULL << ICH_LR_EL2_STATE_SHIFT); 195 static const uint64_t ICH_LR_EL2_STATE_ACTIVE_BIT = 196 (2ULL << ICH_LR_EL2_STATE_SHIFT); | |
197 | 219 |
198 static const uint64_t ICH_LRC_PRIORITY_SHIFT = 199 ICH_LR_EL2_PRIORITY_SHIFT - 32; 200 static const uint64_t ICH_LRC_PRIORITY_LENGTH = 201 ICH_LR_EL2_PRIORITY_LENGTH; | 220 BitUnion32(ICH_LRC) 221 Bitfield<31, 30> State; 222 Bitfield<29> HW; 223 Bitfield<28> Group; 224 Bitfield<27, 24> res0_1; 225 Bitfield<23, 16> Priority; 226 Bitfield<15, 13> res0_0; 227 Bitfield<12, 0> pINTID; 228 Bitfield<9> EOI; 229 EndBitUnion(ICH_LRC) |
202 | 230 |
203 static const uint32_t ICH_MISR_EL2_EOI = (1 << 0); 204 static const uint32_t ICH_MISR_EL2_U = (1 << 1); 205 static const uint32_t ICH_MISR_EL2_LRENP = (1 << 2); 206 static const uint32_t ICH_MISR_EL2_NP = (1 << 3); 207 static const uint32_t ICH_MISR_EL2_VGRP0E = (1 << 4); 208 static const uint32_t ICH_MISR_EL2_VGRP0D = (1 << 5); 209 static const uint32_t ICH_MISR_EL2_VGRP1E = (1 << 6); 210 static const uint32_t ICH_MISR_EL2_VGRP1D = (1 << 7); | 231 BitUnion64(ICH_MISR_EL2) 232 Bitfield<63, 8> res0; 233 Bitfield<7> VGrp1D; 234 Bitfield<6> VGrp1E; 235 Bitfield<5> VGrp0D; 236 Bitfield<4> VGrp0E; 237 Bitfield<3> NP; 238 Bitfield<2> LRENP; 239 Bitfield<1> U; 240 Bitfield<0> EOI; 241 EndBitUnion(ICH_MISR_EL2) |
211 | 242 |
212 static const uint32_t ICH_VMCR_EL2_VENG0_SHIFT = 0; 213 static const uint32_t ICH_VMCR_EL2_VENG0 = 214 (1 << ICH_VMCR_EL2_VENG0_SHIFT); 215 static const uint32_t ICH_VMCR_EL2_VENG1_SHIFT = 1; 216 static const uint32_t ICH_VMCR_EL2_VENG1 = 217 (1 << ICH_VMCR_EL2_VENG1_SHIFT); 218 static const uint32_t ICH_VMCR_EL2_VACKCTL = (1 << 2); 219 static const uint32_t ICH_VMCR_EL2_VFIQEN = (1 << 3); 220 static const uint32_t ICH_VMCR_EL2_VCBPR_SHIFT = 4; 221 static const uint32_t ICH_VMCR_EL2_VCBPR = 222 (1 << ICH_VMCR_EL2_VCBPR_SHIFT); 223 static const uint32_t ICH_VMCR_EL2_VEOIM_SHIFT = 9; 224 static const uint32_t ICH_VMCR_EL2_VEOIM = 225 (1 << ICH_VMCR_EL2_VEOIM_SHIFT); 226 static const uint32_t ICH_VMCR_EL2_VBPR1_SHIFT = 18; 227 static const uint32_t ICH_VMCR_EL2_VBPR1_LENGTH = 3; 228 static const uint32_t ICH_VMCR_EL2_VBPR1_MASK = 229 (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT); 230 static const uint32_t ICH_VMCR_EL2_VBPR0_SHIFT = 21; 231 static const uint32_t ICH_VMCR_EL2_VBPR0_LENGTH = 3; 232 static const uint32_t ICH_VMCR_EL2_VBPR0_MASK = 233 (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT); 234 static const uint32_t ICH_VMCR_EL2_VPMR_SHIFT = 24; 235 static const uint32_t ICH_VMCR_EL2_VPMR_LENGTH = 8; 236 static const uint32_t ICH_VMCR_EL2_VPMR_MASK = 237 (0xffU << ICH_VMCR_EL2_VPMR_SHIFT); | 243 BitUnion64(ICH_VMCR_EL2) 244 Bitfield<63, 32> res0_2; 245 Bitfield<31, 24> VPMR; 246 Bitfield<23, 21> VBPR0; 247 Bitfield<20, 18> VBPR1; 248 Bitfield<17, 10> res0_1; 249 Bitfield<9> VEOIM; 250 Bitfield<8, 5> res0_0; 251 Bitfield<4> VCBPR; 252 Bitfield<3> VFIQEn; 253 Bitfield<2> VAckCtl; 254 Bitfield<1> VENG1; 255 Bitfield<0> VENG0; 256 EndBitUnion(ICH_VMCR_EL2) |
238 | 257 |
239 static const uint32_t ICH_VTR_EL2_LISTREGS_SHIFT = 0; 240 static const uint32_t ICH_VTR_EL2_TDS = 1 << 19; 241 static const uint32_t ICH_VTR_EL2_NV4 = 1 << 20; 242 static const uint32_t ICH_VTR_EL2_A3V = 1 << 21; 243 static const uint32_t ICH_VTR_EL2_SEIS = 1 << 22; 244 static const uint32_t ICH_VTR_EL2_IDBITS_SHIFT = 23; 245 static const uint32_t ICH_VTR_EL2_PREBITS_SHIFT = 26; 246 static const uint32_t ICH_VTR_EL2_PRIBITS_SHIFT = 29; | 258 BitUnion64(ICH_VTR_EL2) 259 Bitfield<63, 32> res0_1; 260 Bitfield<31, 29> PRIbits; 261 Bitfield<28, 26> PREbits; 262 Bitfield<25, 23> IDbits; 263 Bitfield<22> SEIS; 264 Bitfield<21> A3V; 265 Bitfield<20> res1; 266 Bitfield<19> TDS; 267 Bitfield<18, 5> res0_0; 268 Bitfield<4, 0> ListRegs; 269 EndBitUnion(ICH_VTR_EL2) |
247 | 270 |
248 public: | 271 BitUnion64(ICV_CTLR_EL1) 272 Bitfield<63, 19> res0_2; 273 Bitfield<18> RSS; 274 Bitfield<17, 16> res0_1; 275 Bitfield<15> A3V; 276 Bitfield<14> SEIS; 277 Bitfield<13, 11> IDbits; 278 Bitfield<10, 8> PRIbits; 279 Bitfield<7, 2> res0_0; 280 Bitfield<1> EOImode; 281 Bitfield<0> CBPR; 282 EndBitUnion(ICV_CTLR_EL1) |
249 | 283 |
250 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); 251 ~Gicv3CPUInterface(); 252 void init(); 253 void initState(); | 284 protected: |
254 | 285 |
286 void activateIRQ(uint32_t intid, Gicv3::GroupId group); 287 int currEL() const; 288 void deactivateIRQ(uint32_t intid, Gicv3::GroupId group); 289 void dropPriority(Gicv3::GroupId group); 290 uint64_t eoiMaintenanceInterruptStatus() const; 291 bool getHCREL2FMO() const; 292 bool getHCREL2IMO() const; 293 uint32_t getHPPIR0() const; 294 uint32_t getHPPIR1() const; 295 int getHPPVILR() const; 296 bool groupEnabled(Gicv3::GroupId group) const; 297 uint32_t groupPriorityMask(Gicv3::GroupId group) const; 298 bool haveEL(ArmISA::ExceptionLevel el) const; 299 int highestActiveGroup() const; 300 uint8_t highestActivePriority() const; 301 bool hppiCanPreempt() const; 302 bool hppviCanPreempt(int lrIdx) const; 303 bool inSecureState() const; 304 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const; 305 bool isAA64() const; 306 bool isEL3OrMon() const; 307 bool isEOISplitMode() const; 308 bool isSecureBelowEL3() const; 309 ICH_MISR_EL2 maintenanceInterruptStatus() const; |
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255 RegVal readMiscReg(int misc_reg) override; | 310 RegVal readMiscReg(int misc_reg) override; |
256 void setMiscReg(int misc_reg, RegVal val) override; 257 void update(); 258 void virtualUpdate(); 259 | 311 void reset(); |
260 void serialize(CheckpointOut & cp) const override; | 312 void serialize(CheckpointOut & cp) const override; |
313 void setMiscReg(int misc_reg, RegVal val) override; |
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261 void unserialize(CheckpointIn & cp) override; | 314 void unserialize(CheckpointIn & cp) override; |
262 263 protected: 264 265 void reset(); 266 bool hppiCanPreempt(); 267 bool hppviCanPreempt(int lrIdx); 268 bool groupEnabled(Gicv3::GroupId group); 269 uint8_t highestActivePriority(); 270 uint8_t virtualHighestActivePriority(); 271 bool inSecureState(); 272 int currEL(); 273 bool haveEL(ArmISA::ExceptionLevel el); 274 void activateIRQ(uint32_t intid, Gicv3::GroupId group); | 315 void update(); |
275 void virtualActivateIRQ(uint32_t lrIdx); | 316 void virtualActivateIRQ(uint32_t lrIdx); |
276 void deactivateIRQ(uint32_t intid, Gicv3::GroupId group); | |
277 void virtualDeactivateIRQ(int lrIdx); | 317 void virtualDeactivateIRQ(int lrIdx); |
278 uint32_t groupPriorityMask(Gicv3::GroupId group); 279 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group); 280 void dropPriority(Gicv3::GroupId group); | |
281 uint8_t virtualDropPriority(); | 318 uint8_t virtualDropPriority(); |
282 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group); 283 bool isEOISplitMode(); 284 bool virtualIsEOISplitMode(); 285 bool isSecureBelowEL3(); 286 bool inSecureState2(); 287 uint32_t eoiMaintenanceInterruptStatus(uint32_t * misr); 288 uint32_t maintenanceInterruptStatus(); 289 int highestActiveGroup(); 290 bool getHCREL2FMO(); 291 bool getHCREL2IMO(); 292 uint32_t getHPPIR1(); 293 uint32_t getHPPIR0(); 294 int getHPPVILR(); 295 int virtualFindActive(uint32_t intid); | 319 int virtualFindActive(uint32_t intid) const; 320 uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const; 321 uint8_t virtualHighestActivePriority() const; |
296 void virtualIncrementEOICount(); | 322 void virtualIncrementEOICount(); |
297 bool isEL3OrMon(); 298 bool isAA64(); | 323 bool virtualIsEOISplitMode() const; 324 void virtualUpdate(); 325 326 public: 327 328 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); 329 330 void init(); 331 void initState(); |
299}; 300 301#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__ | 332}; 333 334#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__ |