1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 308 unchanged lines hidden (view full) --- 317 bool hppviCanPreempt(int lrIdx) const; 318 bool inSecureState() const; 319 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const; 320 bool isAA64() const; 321 bool isEL3OrMon() const; 322 bool isEOISplitMode() const; 323 bool isSecureBelowEL3() const; 324 ICH_MISR_EL2 maintenanceInterruptStatus() const; |
325 void serialize(CheckpointOut & cp) const override; 326 void unserialize(CheckpointIn & cp) override; 327 void update(); 328 void updateDistributor(); 329 void virtualActivateIRQ(uint32_t lrIdx); 330 void virtualDeactivateIRQ(int lrIdx); 331 uint8_t virtualDropPriority(); 332 int virtualFindActive(uint32_t intid) const; --- 6 unchanged lines hidden (view full) --- 339 340 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const; 341 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const; 342 public: 343 344 Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); 345 346 void init(); |
347 348 public: // BaseISADevice 349 RegVal readMiscReg(int misc_reg) override; 350 void setMiscReg(int misc_reg, RegVal val) override; 351 void setThreadContext(ThreadContext *tc) override; 352}; 353 354#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__ |