gic_v3_cpu_interface.cc (14248:36750190a8ed) gic_v3_cpu_interface.cc (14254:853fe0880d9a)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;
203 }
204
205 // Interrupt Group 1 Enable register EL3
206 case MISCREG_ICC_MGRPEN1:
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;
203 }
204
205 // Interrupt Group 1 Enable register EL3
206 case MISCREG_ICC_MGRPEN1:
207 case MISCREG_ICC_IGRPEN1_EL3:
207 case MISCREG_ICC_IGRPEN1_EL3: {
208 ICC_IGRPEN1_EL3 igrp_el3 = 0;
209 igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
210 MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
211
212 igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
213 MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
214
215 value = igrp_el3;
208 break;
216 break;
217 }
209
210 // Running Priority Register
211 case MISCREG_ICC_RPR:
212 case MISCREG_ICC_RPR_EL1: {
213 if ((currEL() == EL1) && !inSecureState() &&
214 (hcr_imo || hcr_fmo)) {
215 return readMiscReg(MISCREG_ICV_RPR_EL1);
216 }

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1339
1340 // Interrupt Group 1 Enable register EL1
1341 case MISCREG_ICC_IGRPEN1:
1342 case MISCREG_ICC_IGRPEN1_EL1: {
1343 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1344 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1345 }
1346
218
219 // Running Priority Register
220 case MISCREG_ICC_RPR:
221 case MISCREG_ICC_RPR_EL1: {
222 if ((currEL() == EL1) && !inSecureState() &&
223 (hcr_imo || hcr_fmo)) {
224 return readMiscReg(MISCREG_ICV_RPR_EL1);
225 }

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1348
1349 // Interrupt Group 1 Enable register EL1
1350 case MISCREG_ICC_IGRPEN1:
1351 case MISCREG_ICC_IGRPEN1_EL1: {
1352 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1353 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1354 }
1355
1347 if (haveEL(EL3)) {
1348 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
1349 ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
1350 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
1351
1352 if (inSecureState()) {
1353 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
1354 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
1355 } else {
1356 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1357 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1358 }
1359
1360 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1361 icc_igrpen1_el3);
1362 }
1363
1364 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1365 updateDistributor();
1366 return;
1367 }
1368
1369 // Virtual Interrupt Group 1 Enable register
1370 case MISCREG_ICV_IGRPEN1_EL1: {
1371 bool enable = val & 0x1;

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1376 virtualUpdate();
1377 return;
1378 }
1379
1380 // Interrupt Group 1 Enable register
1381 case MISCREG_ICC_MGRPEN1:
1382 case MISCREG_ICC_IGRPEN1_EL3: {
1383 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1356 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1357 updateDistributor();
1358 return;
1359 }
1360
1361 // Virtual Interrupt Group 1 Enable register
1362 case MISCREG_ICV_IGRPEN1_EL1: {
1363 bool enable = val & 0x1;

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1368 virtualUpdate();
1369 return;
1370 }
1371
1372 // Interrupt Group 1 Enable register
1373 case MISCREG_ICC_MGRPEN1:
1374 case MISCREG_ICC_IGRPEN1_EL3: {
1375 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1384 ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
1385 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
1386
1376
1387 if (inSecureState()) {
1388 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
1389 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
1390 } else {
1391 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
1392 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
1393 }
1394
1395 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
1396 break;
1377 isa->setMiscRegNoEffect(
1378 MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
1379 isa->setMiscRegNoEffect(
1380 MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
1381 return;
1397 }
1398
1399 // Software Generated Interrupt Group 0 Register
1400 case MISCREG_ICC_SGI0R:
1401 case MISCREG_ICC_SGI0R_EL1:
1402 generateSGI(val, Gicv3::G0S);
1403 break;
1404

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1383
1384 // Software Generated Interrupt Group 0 Register
1385 case MISCREG_ICC_SGI0R:
1386 case MISCREG_ICC_SGI0R_EL1:
1387 generateSGI(val, Gicv3::G0S);
1388 break;
1389

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