gic_v3_cpu_interface.cc (14247:818e02fbc795) gic_v3_cpu_interface.cc (14248:36750190a8ed)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1316
1317 // Interrupt Group 0 Enable Register EL1
1318 case MISCREG_ICC_IGRPEN0:
1319 case MISCREG_ICC_IGRPEN0_EL1: {
1320 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1321 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1322 }
1323
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1307 unchanged lines hidden (view full) ---

1316
1317 // Interrupt Group 0 Enable Register EL1
1318 case MISCREG_ICC_IGRPEN0:
1319 case MISCREG_ICC_IGRPEN0_EL1: {
1320 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1321 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1322 }
1323
1324 break;
1324 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1325 updateDistributor();
1326 return;
1325 }
1326
1327 // Virtual Interrupt Group 0 Enable register
1328 case MISCREG_ICV_IGRPEN0_EL1: {
1329 bool enable = val & 0x1;
1330 ICH_VMCR_EL2 ich_vmcr_el2 =
1331 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1332 ich_vmcr_el2.VENG0 = enable;

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1355 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1356 }
1357
1358 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1359 icc_igrpen1_el3);
1360 }
1361
1362 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1327 }
1328
1329 // Virtual Interrupt Group 0 Enable register
1330 case MISCREG_ICV_IGRPEN0_EL1: {
1331 bool enable = val & 0x1;
1332 ICH_VMCR_EL2 ich_vmcr_el2 =
1333 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1334 ich_vmcr_el2.VENG0 = enable;

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1357 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1358 }
1359
1360 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1361 icc_igrpen1_el3);
1362 }
1363
1364 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1365 updateDistributor();
1363 return;
1364 }
1365
1366 // Virtual Interrupt Group 1 Enable register
1367 case MISCREG_ICV_IGRPEN1_EL1: {
1368 bool enable = val & 0x1;
1369 ICH_VMCR_EL2 ich_vmcr_el2 =
1370 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);

--- 1233 unchanged lines hidden --- 		1366 return;
1367 }
1368
1369 // Virtual Interrupt Group 1 Enable register
1370 case MISCREG_ICV_IGRPEN1_EL1: {
1371 bool enable = val & 0x1;
1372 ICH_VMCR_EL2 ich_vmcr_el2 =
1373 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);

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