gic_v3_cpu_interface.cc (14246:033f20c96440) gic_v3_cpu_interface.cc (14247:818e02fbc795)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 177 unchanged lines hidden (view full) ---

186
187 // Interrupt Group 1 Enable register EL1
188 case MISCREG_ICC_IGRPEN1:
189 case MISCREG_ICC_IGRPEN1_EL1: {
190 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
191 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
192 }
193
194 value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
194 break;
195 }
196
197 case MISCREG_ICV_IGRPEN1_EL1: {
198 ICH_VMCR_EL2 ich_vmcr_el2 =
199 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
200 value = ich_vmcr_el2.VENG1;
201 break;

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1353 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1354 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1355 }
1356
1357 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1358 icc_igrpen1_el3);
1359 }
1360
195 break;
196 }
197
198 case MISCREG_ICV_IGRPEN1_EL1: {
199 ICH_VMCR_EL2 ich_vmcr_el2 =
200 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
201 value = ich_vmcr_el2.VENG1;
202 break;

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1354 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
1355 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
1356 }
1357
1358 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
1359 icc_igrpen1_el3);
1360 }
1361
1361 break;
1362 setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1363 return;
1362 }
1363
1364 // Virtual Interrupt Group 1 Enable register
1365 case MISCREG_ICV_IGRPEN1_EL1: {
1366 bool enable = val & 0x1;
1367 ICH_VMCR_EL2 ich_vmcr_el2 =
1368 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1369 ich_vmcr_el2.VENG1 = enable;

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1365
1366 // Virtual Interrupt Group 1 Enable register
1367 case MISCREG_ICV_IGRPEN1_EL1: {
1368 bool enable = val & 0x1;
1369 ICH_VMCR_EL2 ich_vmcr_el2 =
1370 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1371 ich_vmcr_el2.VENG1 = enable;

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