gic_v3_cpu_interface.cc (14245:0c0a6fd47628) gic_v3_cpu_interface.cc (14246:033f20c96440)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 114 unchanged lines hidden (view full) ---

123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 114 unchanged lines hidden (view full) ---

123 switch (misc_reg) {
124 // Active Priorities Group 1 Registers
125 case MISCREG_ICC_AP1R0:
126 case MISCREG_ICC_AP1R0_EL1: {
127 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
128 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
129 }
130
131 break;
131 return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:

--- 595 unchanged lines hidden (view full) ---

735 switch (misc_reg) {
736 // Active Priorities Group 1 Registers
737 case MISCREG_ICC_AP1R0:
738 case MISCREG_ICC_AP1R0_EL1:
739 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
740 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
741 }
742
132 }
133
134 case MISCREG_ICC_AP1R1:
135 case MISCREG_ICC_AP1R1_EL1:
136
137 // only implemented if supporting 6 or more bits of priority
138 case MISCREG_ICC_AP1R2:
139 case MISCREG_ICC_AP1R2_EL1:

--- 595 unchanged lines hidden (view full) ---

735 switch (misc_reg) {
736 // Active Priorities Group 1 Registers
737 case MISCREG_ICC_AP1R0:
738 case MISCREG_ICC_AP1R0_EL1:
739 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
740 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
741 }
742
743 break;
743 setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
744 return;
744
745 case MISCREG_ICC_AP1R1:
746 case MISCREG_ICC_AP1R1_EL1:
747
748 // only implemented if supporting 6 or more bits of priority
749 case MISCREG_ICC_AP1R2:
750 case MISCREG_ICC_AP1R2_EL1:
751

--- 962 unchanged lines hidden (view full) ---

1714 }
1715
1716 return hppi.intid;
1717}
1718
1719void
1720Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1721{
745
746 case MISCREG_ICC_AP1R1:
747 case MISCREG_ICC_AP1R1_EL1:
748
749 // only implemented if supporting 6 or more bits of priority
750 case MISCREG_ICC_AP1R2:
751 case MISCREG_ICC_AP1R2_EL1:
752

--- 962 unchanged lines hidden (view full) ---

1715 }
1716
1717 return hppi.intid;
1718}
1719
1720void
1721Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1722{
1722 int apr_misc_reg;
1723 RegVal apr;
1724 apr_misc_reg = group == Gicv3::G0S ?
1725 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1726 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1723 int apr_misc_reg = 0;
1727
1724
1725 switch (group) {
1726 case Gicv3::G0S:
1727 apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
1728 break;
1729 case Gicv3::G1S:
1730 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
1731 break;
1732 case Gicv3::G1NS:
1733 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS;
1734 break;
1735 default:
1736 panic("Invalid Gicv3::GroupId");
1737 }
1738
1739 RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1740
1728 if (apr) {
1729 apr &= apr - 1;
1730 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1731 }
1732
1733 update();
1734}
1735

--- 73 unchanged lines hidden (view full) ---

1809
1810void
1811Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1812{
1813 // Update active priority registers.
1814 uint32_t prio = hppi.prio & 0xf8;
1815 int apr_bit = prio >> (8 - PRIORITY_BITS);
1816 int reg_bit = apr_bit % 32;
1741 if (apr) {
1742 apr &= apr - 1;
1743 isa->setMiscRegNoEffect(apr_misc_reg, apr);
1744 }
1745
1746 update();
1747}
1748

--- 73 unchanged lines hidden (view full) ---

1822
1823void
1824Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1825{
1826 // Update active priority registers.
1827 uint32_t prio = hppi.prio & 0xf8;
1828 int apr_bit = prio >> (8 - PRIORITY_BITS);
1829 int reg_bit = apr_bit % 32;
1817 int apr_idx = group == Gicv3::G0S ?
1818 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1830
1831 int apr_idx = 0;
1832 switch (group) {
1833 case Gicv3::G0S:
1834 apr_idx = MISCREG_ICC_AP0R0_EL1;
1835 break;
1836 case Gicv3::G1S:
1837 apr_idx = MISCREG_ICC_AP1R0_EL1_S;
1838 break;
1839 case Gicv3::G1NS:
1840 apr_idx = MISCREG_ICC_AP1R0_EL1_NS;
1841 break;
1842 default:
1843 panic("Invalid Gicv3::GroupId");
1844 }
1845
1819 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1820 apr |= (1 << reg_bit);
1821 isa->setMiscRegNoEffect(apr_idx, apr);
1822
1823 // Move interrupt state from pending to active.
1824 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1825 // SGI or PPI, redistributor
1826 redistributor->activateIRQ(int_id);

--- 748 unchanged lines hidden --- 		1846 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1847 apr |= (1 << reg_bit);
1848 isa->setMiscRegNoEffect(apr_idx, apr);
1849
1850 // Move interrupt state from pending to active.
1851 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1852 // SGI or PPI, redistributor
1853 redistributor->activateIRQ(int_id);

--- 748 unchanged lines hidden ---