gic_v3_cpu_interface.cc (14243:6116e1413f80) gic_v3_cpu_interface.cc (14245:0c0a6fd47628)
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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548
549 // Control Register
550 case MISCREG_ICC_CTLR:
551 case MISCREG_ICC_CTLR_EL1: {
552 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
553 return readMiscReg(MISCREG_ICV_CTLR_EL1);
554 }
555
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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548
549 // Control Register
550 case MISCREG_ICC_CTLR:
551 case MISCREG_ICC_CTLR_EL1: {
552 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
553 return readMiscReg(MISCREG_ICV_CTLR_EL1);
554 }
555
556 value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
556 // Enforce value for RO bits
557 // ExtRange [19], INTIDs in the range 1024..8191 not supported
558 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
559 // A3V [15], supports non-zero values of the Aff3 field in SGI
560 // generation System registers
561 // SEIS [14], does not support generation of SEIs (deprecated)
562 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
563 // PRIbits [10:8], number of priority bits implemented, minus one

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1127 * RSS is RO.
1128 * A3V is RO.
1129 * SEIS is RO.
1130 * IDbits is RO.
1131 * PRIbits is RO.
1132 */
1133 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1134 ICC_CTLR_EL1 icc_ctlr_el1 =
557 // Enforce value for RO bits
558 // ExtRange [19], INTIDs in the range 1024..8191 not supported
559 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported
560 // A3V [15], supports non-zero values of the Aff3 field in SGI
561 // generation System registers
562 // SEIS [14], does not support generation of SEIs (deprecated)
563 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
564 // PRIbits [10:8], number of priority bits implemented, minus one

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1128 * RSS is RO.
1129 * A3V is RO.
1130 * SEIS is RO.
1131 * IDbits is RO.
1132 * PRIbits is RO.
1133 */
1134 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1135 ICC_CTLR_EL1 icc_ctlr_el1 =
1135 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1136 readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
1136
1137 ICC_CTLR_EL3 icc_ctlr_el3 =
1138 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1139
1140 // The following could be refactored but it is following
1141 // spec description section 9.2.6 point by point.
1142
1143 // PMHE

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1185 }
1186 } else {
1187 // CBPR is RW
1188 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1189 }
1190
1191 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1192
1137
1138 ICC_CTLR_EL3 icc_ctlr_el3 =
1139 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1140
1141 // The following could be refactored but it is following
1142 // spec description section 9.2.6 point by point.
1143
1144 // PMHE

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1186 }
1187 } else {
1188 // CBPR is RW
1189 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR;
1190 }
1191
1192 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
1193
1193 val = icc_ctlr_el1;
1194 break;
1194 setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
1195 return;
1195 }
1196
1197 // Virtual Control Register
1198 case MISCREG_ICV_CTLR_EL1: {
1199 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1200 ICV_CTLR_EL1 icv_ctlr_el1 =
1201 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1202 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;

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1958bool
1959Gicv3CPUInterface::isEOISplitMode() const
1960{
1961 if (isEL3OrMon()) {
1962 ICC_CTLR_EL3 icc_ctlr_el3 =
1963 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1964 return icc_ctlr_el3.EOImode_EL3;
1965 } else {
1196 }
1197
1198 // Virtual Control Register
1199 case MISCREG_ICV_CTLR_EL1: {
1200 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1201 ICV_CTLR_EL1 icv_ctlr_el1 =
1202 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1);
1203 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode;

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1959bool
1960Gicv3CPUInterface::isEOISplitMode() const
1961{
1962 if (isEL3OrMon()) {
1963 ICC_CTLR_EL3 icc_ctlr_el3 =
1964 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1965 return icc_ctlr_el3.EOImode_EL3;
1966 } else {
1966 ICC_CTLR_EL1 icc_ctlr_el1 =
1967 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1967 ICC_CTLR_EL1 icc_ctlr_el1 = 0;
1968 if (inSecureState())
1969 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1970 else
1971 icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1968 return icc_ctlr_el1.EOImode;
1969 }
1970}
1971
1972bool
1973Gicv3CPUInterface::virtualIsEOISplitMode() const
1974{
1975 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);

--- 595 unchanged lines hidden --- 		1972 return icc_ctlr_el1.EOImode;
1973 }
1974}
1975
1976bool
1977Gicv3CPUInterface::virtualIsEOISplitMode() const
1978{
1979 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);

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