| gic_v3_cpu_interface.cc (14233:a2714268f5c1) | gic_v3_cpu_interface.cc (14234:d41acf9cf6dc) |
|---|---|
| 1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 2262 unchanged lines hidden (view full) --- 2271 2272bool 2273Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 2274{ 2275 switch (group) { 2276 case Gicv3::G0S: { 2277 ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 2278 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); | 1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 2262 unchanged lines hidden (view full) --- 2271 2272bool 2273Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 2274{ 2275 switch (group) { 2276 case Gicv3::G0S: { 2277 ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 2278 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); |
| 2279 return icc_igrpen0_el1.Enable; | 2279 return icc_igrpen0_el1.Enable && distributor->EnableGrp0; |
| 2280 } 2281 2282 case Gicv3::G1S: { 2283 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 2284 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); | 2280 } 2281 2282 case Gicv3::G1S: { 2283 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 2284 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); |
| 2285 return icc_igrpen1_el1_s.Enable; | 2285 return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S; |
| 2286 } 2287 2288 case Gicv3::G1NS: { 2289 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 2290 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); | 2286 } 2287 2288 case Gicv3::G1NS: { 2289 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 2290 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); |
| 2291 return icc_igrpen1_el1_ns.Enable; | 2291 return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS; |
| 2292 } 2293 2294 default: 2295 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 2296 } 2297} 2298 2299bool --- 224 unchanged lines hidden --- | 2292 } 2293 2294 default: 2295 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 2296 } 2297} 2298 2299bool --- 224 unchanged lines hidden --- |