gic_v3_cpu_interface.cc (13926:d6ebddee93a7) gic_v3_cpu_interface.cc (14057:786dbd2c3bfc)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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154 case MISCREG_ICC_AP0R3_EL1:
155 // only implemented if supporting 7 or more bits of priority
156 return 0;
157
158 // Interrupt Group 0 Enable register EL1
159 case MISCREG_ICC_IGRPEN0:
160 case MISCREG_ICC_IGRPEN0_EL1: {
161 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 145 unchanged lines hidden (view full) ---

154 case MISCREG_ICC_AP0R3_EL1:
155 // only implemented if supporting 7 or more bits of priority
156 return 0;
157
158 // Interrupt Group 0 Enable register EL1
159 case MISCREG_ICC_IGRPEN0:
160 case MISCREG_ICC_IGRPEN0_EL1: {
161 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
162 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
162 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
163 }
164
165 break;
166 }
167
163 }
164
165 break;
166 }
167
168 case MISCREG_ICV_IGRPEN0_EL1: {
169 ICH_VMCR_EL2 ich_vmcr_el2 =
170 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
171 value = ich_vmcr_el2.VENG0;
172 break;
173 }
174
168 // Interrupt Group 1 Enable register EL1
169 case MISCREG_ICC_IGRPEN1:
170 case MISCREG_ICC_IGRPEN1_EL1: {
171 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
175 // Interrupt Group 1 Enable register EL1
176 case MISCREG_ICC_IGRPEN1:
177 case MISCREG_ICC_IGRPEN1_EL1: {
178 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
172 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
179 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
173 }
174
175 break;
176 }
177
180 }
181
182 break;
183 }
184
185 case MISCREG_ICV_IGRPEN1_EL1: {
186 ICH_VMCR_EL2 ich_vmcr_el2 =
187 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
188 value = ich_vmcr_el2.VENG1;
189 break;
190 }
191
178 // Interrupt Group 1 Enable register EL3
179 case MISCREG_ICC_MGRPEN1:
180 case MISCREG_ICC_IGRPEN1_EL3:
181 break;
182
183 // Running Priority Register
184 case MISCREG_ICC_RPR:
185 case MISCREG_ICC_RPR_EL1: {

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375 value = vbpr;
376 break;
377 }
378
379 // Interrupt Priority Mask Register
380 case MISCREG_ICC_PMR:
381 case MISCREG_ICC_PMR_EL1:
382 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
192 // Interrupt Group 1 Enable register EL3
193 case MISCREG_ICC_MGRPEN1:
194 case MISCREG_ICC_IGRPEN1_EL3:
195 break;
196
197 // Running Priority Register
198 case MISCREG_ICC_RPR:
199 case MISCREG_ICC_RPR_EL1: {

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389 value = vbpr;
390 break;
391 }
392
393 // Interrupt Priority Mask Register
394 case MISCREG_ICC_PMR:
395 case MISCREG_ICC_PMR_EL1:
396 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
383 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
397 return readMiscReg(MISCREG_ICV_PMR_EL1);
384 }
385
386 if (haveEL(EL3) && !inSecureState() &&
387 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
388 // Spec section 4.8.1
389 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
390 if ((value & 0x80) == 0) {
391 // If the current priority mask value is in the range of

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396 // 0x80-0xFF a read access returns the Non-secure read of the
397 // current value.
398 value = (value << 1) & 0xff;
399 }
400 }
401
402 break;
403
398 }
399
400 if (haveEL(EL3) && !inSecureState() &&
401 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
402 // Spec section 4.8.1
403 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
404 if ((value & 0x80) == 0) {
405 // If the current priority mask value is in the range of

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410 // 0x80-0xFF a read access returns the Non-secure read of the
411 // current value.
412 value = (value << 1) & 0xff;
413 }
414 }
415
416 break;
417
418 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
419 ICH_VMCR_EL2 ich_vmcr_el2 =
420 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
421
422 value = ich_vmcr_el2.VPMR;
423 break;
424 }
425
404 // Interrupt Acknowledge Register 0
405 case MISCREG_ICC_IAR0:
406 case MISCREG_ICC_IAR0_EL1: {
407 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
408 return readMiscReg(MISCREG_ICV_IAR0_EL1);
409 }
410
411 uint32_t int_id;

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1268 val = icc_ctlr_el3;
1269 break;
1270 }
1271
1272 // Priority Mask Register
1273 case MISCREG_ICC_PMR:
1274 case MISCREG_ICC_PMR_EL1: {
1275 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
426 // Interrupt Acknowledge Register 0
427 case MISCREG_ICC_IAR0:
428 case MISCREG_ICC_IAR0_EL1: {
429 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
430 return readMiscReg(MISCREG_ICV_IAR0_EL1);
431 }
432
433 uint32_t int_id;

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1290 val = icc_ctlr_el3;
1291 break;
1292 }
1293
1294 // Priority Mask Register
1295 case MISCREG_ICC_PMR:
1296 case MISCREG_ICC_PMR_EL1: {
1297 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
1276 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1298 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1277 }
1278
1279 val &= 0xff;
1280 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1281
1282 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1283 // Spec section 4.8.1
1284 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:

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1298
1299 val = (val >> 1) | 0x80;
1300 }
1301
1302 val &= ~0U << (8 - PRIORITY_BITS);
1303 break;
1304 }
1305
1299 }
1300
1301 val &= 0xff;
1302 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1303
1304 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1305 // Spec section 4.8.1
1306 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:

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1320
1321 val = (val >> 1) | 0x80;
1322 }
1323
1324 val &= ~0U << (8 - PRIORITY_BITS);
1325 break;
1326 }
1327
1328 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1329 ICH_VMCR_EL2 ich_vmcr_el2 =
1330 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1331 ich_vmcr_el2.VPMR = val & 0xff;
1332
1333 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1334 virtualUpdate();
1335 return;
1336 }
1337
1306 // Interrupt Group 0 Enable Register EL1
1307 case MISCREG_ICC_IGRPEN0:
1308 case MISCREG_ICC_IGRPEN0_EL1: {
1309 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1310 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1311 }
1312
1313 break;

--- 1158 unchanged lines hidden --- 		1338 // Interrupt Group 0 Enable Register EL1
1339 case MISCREG_ICC_IGRPEN0:
1340 case MISCREG_ICC_IGRPEN0_EL1: {
1341 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1342 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1343 }
1344
1345 break;

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