gic_v3_cpu_interface.cc (13923:a7d1f05a0477) gic_v3_cpu_interface.cc (13926:d6ebddee93a7)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "dev/arm/gic_v3_cpu_interface.hh"
32
33#include "arch/arm/isa.hh"
34#include "debug/GIC.hh"
35#include "dev/arm/gic_v3.hh"
36#include "dev/arm/gic_v3_distributor.hh"
37#include "dev/arm/gic_v3_redistributor.hh"
38
39const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
40const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
41
39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
40 : BaseISADevice(),
41 gic(gic),
42 redistributor(nullptr),
43 distributor(nullptr),
44 cpuId(cpu_id)
45{
46}

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317 }
318
319 uint8_t bpr;
320
321 if (group == Gicv3::G0S) {
322 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
323 } else {
324 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
42Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
43 : BaseISADevice(),
44 gic(gic),
45 redistributor(nullptr),
46 distributor(nullptr),
47 cpuId(cpu_id)
48{
49}

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320 }
321
322 uint8_t bpr;
323
324 if (group == Gicv3::G0S) {
325 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
326 } else {
327 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
328 bpr = std::max(bpr, group == Gicv3::G1S ?
329 GIC_MIN_BPR : GIC_MIN_BPR_NS);
325 }
326
327 if (sat_inc) {
328 bpr++;
329
330 if (bpr > 7) {
331 bpr = 7;
332 }

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1839 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1840}
1841
1842/*
1843 * Returns the priority group field for the current BPR value for the group.
1844 * GroupBits() Pseudocode from spec.
1845 */
1846uint32_t
330 }
331
332 if (sat_inc) {
333 bpr++;
334
335 if (bpr > 7) {
336 bpr = 7;
337 }

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1844 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
1845}
1846
1847/*
1848 * Returns the priority group field for the current BPR value for the group.
1849 * GroupBits() Pseudocode from spec.
1850 */
1851uint32_t
1847Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
1852Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
1848{
1849 ICC_CTLR_EL1 icc_ctlr_el1_s =
1850 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1851 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1852 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1853
1854 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1855 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1856 group = Gicv3::G0S;
1857 }
1858
1859 int bpr;
1860
1861 if (group == Gicv3::G0S) {
1853{
1854 ICC_CTLR_EL1 icc_ctlr_el1_s =
1855 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1856 ICC_CTLR_EL1 icc_ctlr_el1_ns =
1857 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1858
1859 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) ||
1860 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) {
1861 group = Gicv3::G0S;
1862 }
1863
1864 int bpr;
1865
1866 if (group == Gicv3::G0S) {
1862 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
1867 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
1863 } else {
1868 } else {
1864 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
1869 bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
1865 }
1866
1867 if (group == Gicv3::G1NS) {
1868 assert(bpr > 0);
1869 bpr--;
1870 }
1871
1872 return ~0U << (bpr + 1);

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2160 if (is_fiq) {
2161 return ArmISA::INT_FIQ;
2162 } else {
2163 return ArmISA::INT_IRQ;
2164 }
2165}
2166
2167bool
1870 }
1871
1872 if (group == Gicv3::G1NS) {
1873 assert(bpr > 0);
1874 bpr--;
1875 }
1876
1877 return ~0U << (bpr + 1);

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2165 if (is_fiq) {
2166 return ArmISA::INT_FIQ;
2167 } else {
2168 return ArmISA::INT_IRQ;
2169 }
2170}
2171
2172bool
2168Gicv3CPUInterface::hppiCanPreempt() const
2173Gicv3CPUInterface::hppiCanPreempt()
2169{
2170 if (hppi.prio == 0xff) {
2171 // there is no pending interrupt
2172 return false;
2173 }
2174
2175 if (!groupEnabled(hppi.group)) {
2176 // group disabled at CPU interface

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2175 if (hppi.prio == 0xff) {
2176 // there is no pending interrupt
2177 return false;
2178 }
2179
2180 if (!groupEnabled(hppi.group)) {
2181 // group disabled at CPU interface

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