gic_v3_cpu_interface.cc (13826:34a9929c35eb) gic_v3_cpu_interface.cc (13923:a7d1f05a0477)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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404 }
405
406 uint32_t int_id;
407
408 if (hppiCanPreempt()) {
409 int_id = getHPPIR0();
410
411 // avoid activation for special interrupts
412 if (int_id < Gicv3::INTID_SECURE) {
412 if (int_id < Gicv3::INTID_SECURE ||
413 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
413 activateIRQ(int_id, hppi.group);
414 }
415 } else {
416 int_id = Gicv3::INTID_SPURIOUS;
417 }
418
419 value = int_id;
420 break;

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459 }
460
461 uint32_t int_id;
462
463 if (hppiCanPreempt()) {
464 int_id = getHPPIR1();
465
466 // avoid activation for special interrupts
414 activateIRQ(int_id, hppi.group);
415 }
416 } else {
417 int_id = Gicv3::INTID_SPURIOUS;
418 }
419
420 value = int_id;
421 break;

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460 }
461
462 uint32_t int_id;
463
464 if (hppiCanPreempt()) {
465 int_id = getHPPIR1();
466
467 // avoid activation for special interrupts
467 if (int_id < Gicv3::INTID_SECURE) {
468 if (int_id < Gicv3::INTID_SECURE ||
469 int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
468 activateIRQ(int_id, hppi.group);
469 }
470 } else {
471 int_id = Gicv3::INTID_SPURIOUS;
472 }
473
474 value = int_id;
475 break;

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773 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
774 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
775 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
776 }
777
778 int int_id = val & 0xffffff;
779
780 // avoid activation for special interrupts
470 activateIRQ(int_id, hppi.group);
471 }
472 } else {
473 int_id = Gicv3::INTID_SPURIOUS;
474 }
475
476 value = int_id;
477 break;

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775 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
776 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
777 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
778 }
779
780 int int_id = val & 0xffffff;
781
782 // avoid activation for special interrupts
781 if (int_id >= Gicv3::INTID_SECURE) {
783 if (int_id >= Gicv3::INTID_SECURE &&
784 int_id <= Gicv3::INTID_SPURIOUS) {
782 return;
783 }
784
785 Gicv3::GroupId group = Gicv3::G0S;
786
787 if (highestActiveGroup() != group) {
788 return;
789 }

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842 case MISCREG_ICC_EOIR1_EL1: {
843 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
844 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
845 }
846
847 int int_id = val & 0xffffff;
848
849 // avoid deactivation for special interrupts
785 return;
786 }
787
788 Gicv3::GroupId group = Gicv3::G0S;
789
790 if (highestActiveGroup() != group) {
791 return;
792 }

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845 case MISCREG_ICC_EOIR1_EL1: {
846 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
847 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
848 }
849
850 int int_id = val & 0xffffff;
851
852 // avoid deactivation for special interrupts
850 if (int_id >= Gicv3::INTID_SECURE) {
853 if (int_id >= Gicv3::INTID_SECURE &&
854 int_id <= Gicv3::INTID_SPURIOUS) {
851 return;
852 }
853
854 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
855
856 if (highestActiveGroup() == Gicv3::G0S) {
857 return;
858 }

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1765 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1766 // SGI or PPI, redistributor
1767 redistributor->activateIRQ(int_id);
1768 redistributor->updateAndInformCPUInterface();
1769 } else if (int_id < Gicv3::INTID_SECURE) {
1770 // SPI, distributor
1771 distributor->activateIRQ(int_id);
1772 distributor->updateAndInformCPUInterfaces();
855 return;
856 }
857
858 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
859
860 if (highestActiveGroup() == Gicv3::G0S) {
861 return;
862 }

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1769 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1770 // SGI or PPI, redistributor
1771 redistributor->activateIRQ(int_id);
1772 redistributor->updateAndInformCPUInterface();
1773 } else if (int_id < Gicv3::INTID_SECURE) {
1774 // SPI, distributor
1775 distributor->activateIRQ(int_id);
1776 distributor->updateAndInformCPUInterfaces();
1777 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
1778 // LPI, Redistributor
1779 redistributor->setClrLPI(int_id, false);
1773 }
1774}
1775
1776void
1777Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1778{
1779 // Update active priority registers.
1780 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +

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1801 // SGI or PPI, redistributor
1802 redistributor->deactivateIRQ(int_id);
1803 redistributor->updateAndInformCPUInterface();
1804 } else if (int_id < Gicv3::INTID_SECURE) {
1805 // SPI, distributor
1806 distributor->deactivateIRQ(int_id);
1807 distributor->updateAndInformCPUInterfaces();
1808 } else {
1780 }
1781}
1782
1783void
1784Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1785{
1786 // Update active priority registers.
1787 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +

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1808 // SGI or PPI, redistributor
1809 redistributor->deactivateIRQ(int_id);
1810 redistributor->updateAndInformCPUInterface();
1811 } else if (int_id < Gicv3::INTID_SECURE) {
1812 // SPI, distributor
1813 distributor->deactivateIRQ(int_id);
1814 distributor->updateAndInformCPUInterfaces();
1815 } else {
1809 return;
1816 // LPI, redistributor, shouldn't deactivate
1817 redistributor->updateAndInformCPUInterface();
1810 }
1811}
1812
1813void
1814Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1815{
1816 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1817 lr_idx);

--- 641 unchanged lines hidden --- 		1818 }
1819}
1820
1821void
1822Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1823{
1824 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1825 lr_idx);

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