gic_v3_cpu_interface.cc (13739:616ef27b6d2e) gic_v3_cpu_interface.cc (13740:7bb2759e56ed)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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383 value = vbpr;
384 break;
385 }
386
387 case MISCREG_ICC_PMR:
388 case MISCREG_ICC_PMR_EL1: // Priority Mask Register
389 if ((currEL() == EL1) && !inSecureState() &&
390 (hcr_imo || hcr_fmo)) {
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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383 value = vbpr;
384 break;
385 }
386
387 case MISCREG_ICC_PMR:
388 case MISCREG_ICC_PMR_EL1: // Priority Mask Register
389 if ((currEL() == EL1) && !inSecureState() &&
390 (hcr_imo || hcr_fmo)) {
391 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
391 return readMiscReg(MISCREG_ICV_PMR_EL1);
392 }
393
394 if (haveEL(EL3) && !inSecureState() &&
395 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
396 /* NS GIC access and Group 0 is inaccessible to NS */
397 if ((value & 0x80) == 0) {
398 /* NS should not see priorities in the Secure half of the
399 * range */
400 value = 0;
401 } else if (value != 0xff) {
402 /* Non-idle priority: show the Non-secure view of it */
403 value = (value << 1) & 0xff;
404 }
405 }
406
407 break;
408
392 }
393
394 if (haveEL(EL3) && !inSecureState() &&
395 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
396 /* NS GIC access and Group 0 is inaccessible to NS */
397 if ((value & 0x80) == 0) {
398 /* NS should not see priorities in the Secure half of the
399 * range */
400 value = 0;
401 } else if (value != 0xff) {
402 /* Non-idle priority: show the Non-secure view of it */
403 value = (value << 1) & 0xff;
404 }
405 }
406
407 break;
408
409 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
410 RegVal ich_vmcr_el2 =
411 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
412
413 value = ich_vmcr_el2 >> ICH_VMCR_EL2_VPMR_SHIFT;
414 break;
415 }
416
409 case MISCREG_ICC_IAR0:
410 case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
411 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
412 return readMiscReg(MISCREG_ICV_IAR0_EL1);
413 }
414
415 uint32_t int_id;
416

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1263 (val & (ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM));
1264 break;
1265 }
1266
1267 case MISCREG_ICC_PMR:
1268 case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
1269 if ((currEL() == EL1) && !inSecureState() &&
1270 (hcr_imo || hcr_fmo)) {
417 case MISCREG_ICC_IAR0:
418 case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
419 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
420 return readMiscReg(MISCREG_ICV_IAR0_EL1);
421 }
422
423 uint32_t int_id;
424

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1271 (val & (ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM));
1272 break;
1273 }
1274
1275 case MISCREG_ICC_PMR:
1276 case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
1277 if ((currEL() == EL1) && !inSecureState() &&
1278 (hcr_imo || hcr_fmo)) {
1271 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
1279 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1272 }
1273
1274 val &= 0xff;
1275 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1276
1277 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1278 /*
1279 * NS access and Group 0 is inaccessible to NS: return the

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1290
1291 val = (val >> 1) | 0x80;
1292 }
1293
1294 val &= ~0U << (8 - PRIORITY_BITS);
1295 break;
1296 }
1297
1280 }
1281
1282 val &= 0xff;
1283 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1284
1285 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1286 /*
1287 * NS access and Group 0 is inaccessible to NS: return the

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1298
1299 val = (val >> 1) | 0x80;
1300 }
1301
1302 val &= ~0U << (8 - PRIORITY_BITS);
1303 break;
1304 }
1305
1306 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1307 RegVal ich_vmcr_el2 =
1308 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1309 ich_vmcr_el2 = insertBits(
1310 ich_vmcr_el2,
1311 ICH_VMCR_EL2_VPMR_SHIFT + ICH_VMCR_EL2_VPMR_LENGTH - 1,
1312 ICH_VMCR_EL2_VPMR_SHIFT, val);
1313
1314 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1315 virtualUpdate();
1316 return;
1317 }
1318
1298 case MISCREG_ICC_IGRPEN0:
1299 case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
1300 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1301 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1302 }
1303
1304 break;
1305 }

--- 1069 unchanged lines hidden --- 		1319 case MISCREG_ICC_IGRPEN0:
1320 case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
1321 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1322 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1323 }
1324
1325 break;
1326 }

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