gic_v3_cpu_interface.cc (13690:284050bbec68) gic_v3_cpu_interface.cc (13739:616ef27b6d2e)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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146 case MISCREG_ICC_AP0R3:
147 case MISCREG_ICC_AP0R3_EL1:
148 // only implemented if supporting 7 or more bits of priority
149 return 0;
150
151 case MISCREG_ICC_IGRPEN0:
152 case MISCREG_ICC_IGRPEN0_EL1: {
153 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 137 unchanged lines hidden (view full) ---

146 case MISCREG_ICC_AP0R3:
147 case MISCREG_ICC_AP0R3_EL1:
148 // only implemented if supporting 7 or more bits of priority
149 return 0;
150
151 case MISCREG_ICC_IGRPEN0:
152 case MISCREG_ICC_IGRPEN0_EL1: {
153 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
154 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
154 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
155 }
156
157 break;
158 }
159
155 }
156
157 break;
158 }
159
160 case MISCREG_ICV_IGRPEN0_EL1: {
161 RegVal ich_vmcr_el2 =
162 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
163 value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG0_SHIFT);
164 break;
165 }
166
160 case MISCREG_ICC_IGRPEN1:
161 case MISCREG_ICC_IGRPEN1_EL1: {
162 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
167 case MISCREG_ICC_IGRPEN1:
168 case MISCREG_ICC_IGRPEN1_EL1: {
169 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
163 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
170 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
164 }
165
166 break;
167 }
168
171 }
172
173 break;
174 }
175
176 case MISCREG_ICV_IGRPEN1_EL1: {
177 RegVal ich_vmcr_el2 =
178 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
179 value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG1_SHIFT);
180 break;
181 }
182
169 case MISCREG_ICC_MGRPEN1:
170 case MISCREG_ICC_IGRPEN1_EL3: {
171 // EnableGrp1S and EnableGrp1NS are aliased with
172 // ICC_IGRPEN1_EL1_S.Enable and ICC_IGRPEN1_EL1_NS.Enable
173 bool enable_grp_1s =
174 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S) &
175 ICC_IGRPEN1_EL1_ENABLE;
176 bool enable_grp_1ns =

--- 2184 unchanged lines hidden --- 		183 case MISCREG_ICC_MGRPEN1:
184 case MISCREG_ICC_IGRPEN1_EL3: {
185 // EnableGrp1S and EnableGrp1NS are aliased with
186 // ICC_IGRPEN1_EL1_S.Enable and ICC_IGRPEN1_EL1_NS.Enable
187 bool enable_grp_1s =
188 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S) &
189 ICC_IGRPEN1_EL1_ENABLE;
190 bool enable_grp_1ns =

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