gic_v3_cpu_interface.cc (13531:e6f1bf55d038) gic_v3_cpu_interface.cc (13580:18ed3315bdb6)
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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91 return false;
92 } else if (hcr.tge) {
93 return true;
94 } else {
95 return hcr.imo;
96 }
97}
98
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 82 unchanged lines hidden (view full) ---

91 return false;
92 } else if (hcr.tge) {
93 return true;
94 } else {
95 return hcr.imo;
96 }
97}
98
99ArmISA::MiscReg
99RegVal
100Gicv3CPUInterface::readMiscReg(int misc_reg)
101{
100Gicv3CPUInterface::readMiscReg(int misc_reg)
101{
102 ArmISA::MiscReg value = isa->readMiscRegNoEffect(misc_reg);
102 RegVal value = isa->readMiscRegNoEffect(misc_reg);
103 bool hcr_fmo = getHCREL2FMO();
104 bool hcr_imo = getHCREL2IMO();
105
106 switch (misc_reg) {
107 case MISCREG_ICC_AP1R0:
108 case MISCREG_ICC_AP1R0_EL1: {
109 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
110 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);

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230 break;
231 }
232
233 case MISCREG_ICV_HPPIR0_EL1: {
234 value = Gicv3::INTID_SPURIOUS;
235 int lr_idx = getHPPVILR();
236
237 if (lr_idx >= 0) {
103 bool hcr_fmo = getHCREL2FMO();
104 bool hcr_imo = getHCREL2IMO();
105
106 switch (misc_reg) {
107 case MISCREG_ICC_AP1R0:
108 case MISCREG_ICC_AP1R0_EL1: {
109 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
110 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);

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230 break;
231 }
232
233 case MISCREG_ICV_HPPIR0_EL1: {
234 value = Gicv3::INTID_SPURIOUS;
235 int lr_idx = getHPPVILR();
236
237 if (lr_idx >= 0) {
238 ArmISA::MiscReg lr =
238 RegVal lr =
239 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
240 Gicv3::GroupId group =
241 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
242
243 if (group == Gicv3::G0S) {
244 value = bits(lr, 31, 0);
245 }
246 }

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258 break;
259 }
260
261 case MISCREG_ICV_HPPIR1_EL1: {
262 value = Gicv3::INTID_SPURIOUS;
263 int lr_idx = getHPPVILR();
264
265 if (lr_idx >= 0) {
239 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
240 Gicv3::GroupId group =
241 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
242
243 if (group == Gicv3::G0S) {
244 value = bits(lr, 31, 0);
245 }
246 }

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258 break;
259 }
260
261 case MISCREG_ICV_HPPIR1_EL1: {
262 value = Gicv3::INTID_SPURIOUS;
263 int lr_idx = getHPPVILR();
264
265 if (lr_idx >= 0) {
266 ArmISA::MiscReg lr =
266 RegVal lr =
267 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
268 Gicv3::GroupId group =
269 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
270
271 if (group == Gicv3::G1NS) {
272 value = bits(lr, 31, 0);
273 }
274 }

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335 value = bpr;
336 break;
337 }
338
339 case MISCREG_ICV_BPR0_EL1:
340 case MISCREG_ICV_BPR1_EL1: {
341 Gicv3::GroupId group =
342 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
267 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
268 Gicv3::GroupId group =
269 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
270
271 if (group == Gicv3::G1NS) {
272 value = bits(lr, 31, 0);
273 }
274 }

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335 value = bpr;
336 break;
337 }
338
339 case MISCREG_ICV_BPR0_EL1:
340 case MISCREG_ICV_BPR1_EL1: {
341 Gicv3::GroupId group =
342 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
343 ArmISA::MiscReg ich_vmcr_el2 =
343 RegVal ich_vmcr_el2 =
344 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
345 bool sat_inc = false;
346
347 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
348 // reads return bpr0 + 1 saturated to 7, writes ignored
349 group = Gicv3::G0S;
350 sat_inc = true;
351 }

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415 break;
416 }
417
418 case MISCREG_ICV_IAR0_EL1: {
419 int lr_idx = getHPPVILR();
420 uint32_t int_id = Gicv3::INTID_SPURIOUS;
421
422 if (lr_idx >= 0) {
344 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
345 bool sat_inc = false;
346
347 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
348 // reads return bpr0 + 1 saturated to 7, writes ignored
349 group = Gicv3::G0S;
350 sat_inc = true;
351 }

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415 break;
416 }
417
418 case MISCREG_ICV_IAR0_EL1: {
419 int lr_idx = getHPPVILR();
420 uint32_t int_id = Gicv3::INTID_SPURIOUS;
421
422 if (lr_idx >= 0) {
423 ArmISA::MiscReg lr =
423 RegVal lr =
424 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
425
426 if (!(lr & ICH_LR_EL2_GROUP) && hppviCanPreempt(lr_idx)) {
427 int_id = value = bits(lr, 31, 0);
428
429 if (int_id < Gicv3::INTID_SECURE ||
430 int_id > Gicv3::INTID_SPURIOUS) {
431 virtualActivateIRQ(lr_idx);

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468 break;
469 }
470
471 case MISCREG_ICV_IAR1_EL1: {
472 int lr_idx = getHPPVILR();
473 uint32_t int_id = Gicv3::INTID_SPURIOUS;
474
475 if (lr_idx >= 0) {
424 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
425
426 if (!(lr & ICH_LR_EL2_GROUP) && hppviCanPreempt(lr_idx)) {
427 int_id = value = bits(lr, 31, 0);
428
429 if (int_id < Gicv3::INTID_SECURE ||
430 int_id > Gicv3::INTID_SPURIOUS) {
431 virtualActivateIRQ(lr_idx);

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468 break;
469 }
470
471 case MISCREG_ICV_IAR1_EL1: {
472 int lr_idx = getHPPVILR();
473 uint32_t int_id = Gicv3::INTID_SPURIOUS;
474
475 if (lr_idx >= 0) {
476 ArmISA::MiscReg lr =
476 RegVal lr =
477 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
478
479 if (lr & ICH_LR_EL2_GROUP && hppviCanPreempt(lr_idx)) {
480 int_id = value = bits(lr, 31, 0);
481
482 if (int_id < Gicv3::INTID_SECURE ||
483 int_id > Gicv3::INTID_SPURIOUS) {
484 virtualActivateIRQ(lr_idx);

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501 case MISCREG_ICC_SRE:
502 case MISCREG_ICC_SRE_EL1: { // System Register Enable Register
503 bool dfb;
504 bool dib;
505
506 if (haveEL(EL3) && !distributor->DS) {
507 // DIB is RO alias of ICC_SRE_EL3.DIB
508 // DFB is RO alias of ICC_SRE_EL3.DFB
477 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
478
479 if (lr & ICH_LR_EL2_GROUP && hppviCanPreempt(lr_idx)) {
480 int_id = value = bits(lr, 31, 0);
481
482 if (int_id < Gicv3::INTID_SECURE ||
483 int_id > Gicv3::INTID_SPURIOUS) {
484 virtualActivateIRQ(lr_idx);

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501 case MISCREG_ICC_SRE:
502 case MISCREG_ICC_SRE_EL1: { // System Register Enable Register
503 bool dfb;
504 bool dib;
505
506 if (haveEL(EL3) && !distributor->DS) {
507 // DIB is RO alias of ICC_SRE_EL3.DIB
508 // DFB is RO alias of ICC_SRE_EL3.DFB
509 ArmISA::MiscReg icc_sre_el3 =
509 RegVal icc_sre_el3 =
510 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
511 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
512 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
513 } else if (haveEL(EL3) && distributor->DS) {
514 // DIB is RW alias of ICC_SRE_EL3.DIB
515 // DFB is RW alias of ICC_SRE_EL3.DFB
510 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
511 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
512 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
513 } else if (haveEL(EL3) && distributor->DS) {
514 // DIB is RW alias of ICC_SRE_EL3.DIB
515 // DFB is RW alias of ICC_SRE_EL3.DFB
516 ArmISA::MiscReg icc_sre_el3 =
516 RegVal icc_sre_el3 =
517 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
518 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
519 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
520 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
521 // DIB is RO alias of ICC_SRE_EL2.DIB
522 // DFB is RO alias of ICC_SRE_EL2.DFB
517 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
518 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
519 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
520 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
521 // DIB is RO alias of ICC_SRE_EL2.DIB
522 // DFB is RO alias of ICC_SRE_EL2.DFB
523 ArmISA::MiscReg icc_sre_el2 =
523 RegVal icc_sre_el2 =
524 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL2);
525 dfb = icc_sre_el2 & ICC_SRE_EL2_DFB;
526 dib = icc_sre_el2 & ICC_SRE_EL2_DIB;
527 } else {
528 dfb = value & ICC_SRE_EL1_DFB;
529 dib = value & ICC_SRE_EL1_DIB;
530 }
531

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583 value |= ICC_CTLR_EL1_RSS | ICC_CTLR_EL1_A3V |
584 (1 << 11) | ((PRIORITY_BITS - 1) << 8);
585 break;
586 }
587
588 case MISCREG_ICV_CTLR_EL1: {
589 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
590 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
524 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL2);
525 dfb = icc_sre_el2 & ICC_SRE_EL2_DFB;
526 dib = icc_sre_el2 & ICC_SRE_EL2_DIB;
527 } else {
528 dfb = value & ICC_SRE_EL1_DFB;
529 dib = value & ICC_SRE_EL1_DIB;
530 }
531

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583 value |= ICC_CTLR_EL1_RSS | ICC_CTLR_EL1_A3V |
584 (1 << 11) | ((PRIORITY_BITS - 1) << 8);
585 break;
586 }
587
588 case MISCREG_ICV_CTLR_EL1: {
589 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
590 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
591 ArmISA::MiscReg ich_vmcr_el2 =
591 RegVal ich_vmcr_el2 =
592 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
593
594 if (ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
595 value |= ICC_CTLR_EL1_EOIMODE;
596 }
597
598 if (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
599 value |= ICC_CTLR_EL1_CBPR;

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607 // Add value for RO bits
608 // RSS [18]
609 // A3V [15]
610 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
611 // PRIbits [10:8], number of priority bits implemented, minus one
612 value |= ICC_CTLR_EL3_RSS | ICC_CTLR_EL3_A3V | (0 << 11) |
613 ((PRIORITY_BITS - 1) << 8);
614 // Aliased bits...
592 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
593
594 if (ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
595 value |= ICC_CTLR_EL1_EOIMODE;
596 }
597
598 if (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
599 value |= ICC_CTLR_EL1_CBPR;

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607 // Add value for RO bits
608 // RSS [18]
609 // A3V [15]
610 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
611 // PRIbits [10:8], number of priority bits implemented, minus one
612 value |= ICC_CTLR_EL3_RSS | ICC_CTLR_EL3_A3V | (0 << 11) |
613 ((PRIORITY_BITS - 1) << 8);
614 // Aliased bits...
615 ArmISA::MiscReg icc_ctlr_el1_ns =
615 RegVal icc_ctlr_el1_ns =
616 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
616 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
617 ArmISA::MiscReg icc_ctlr_el1_s =
617 RegVal icc_ctlr_el1_s =
618 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
619
620 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_EOIMODE) {
621 value |= ICC_CTLR_EL3_EOIMODE_EL1NS;
622 }
623
624 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_CBPR) {
625 value |= ICC_CTLR_EL3_CBPR_EL1NS;

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648 case MISCREG_ICH_AP1R0_EL2:
649 break;
650
651 case MISCREG_ICH_MISR:
652 case MISCREG_ICH_MISR_EL2: {
653 value = 0;
654 // Scan list registers and fill in the U, NP and EOI bits
655 eoiMaintenanceInterruptStatus((uint32_t *) &value);
618 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
619
620 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_EOIMODE) {
621 value |= ICC_CTLR_EL3_EOIMODE_EL1NS;
622 }
623
624 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_CBPR) {
625 value |= ICC_CTLR_EL3_CBPR_EL1NS;

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648 case MISCREG_ICH_AP1R0_EL2:
649 break;
650
651 case MISCREG_ICH_MISR:
652 case MISCREG_ICH_MISR_EL2: {
653 value = 0;
654 // Scan list registers and fill in the U, NP and EOI bits
655 eoiMaintenanceInterruptStatus((uint32_t *) &value);
656 ArmISA::MiscReg ich_hcr_el2 =
656 RegVal ich_hcr_el2 =
657 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
657 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
658 ArmISA::MiscReg ich_vmcr_el2 =
658 RegVal ich_vmcr_el2 =
659 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
660
661 if (ich_hcr_el2 &
662 (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
663 value |= ICH_MISR_EL2_LRENP;
664 }
665
666 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&

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718 value = eoiMaintenanceInterruptStatus(nullptr);
719 break;
720
721 case MISCREG_ICH_ELRSR:
722 case MISCREG_ICH_ELRSR_EL2:
723 value = 0;
724
725 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
659 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
660
661 if (ich_hcr_el2 &
662 (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
663 value |= ICH_MISR_EL2_LRENP;
664 }
665
666 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&

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718 value = eoiMaintenanceInterruptStatus(nullptr);
719 break;
720
721 case MISCREG_ICH_ELRSR:
722 case MISCREG_ICH_ELRSR_EL2:
723 value = 0;
724
725 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
726 ArmISA::MiscReg lr =
726 RegVal lr =
727 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
728
729 if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
730 ((lr & ICH_LR_EL2_HW) != 0 ||
731 (lr & ICH_LR_EL2_EOI) == 0)) {
732 value |= (1 << lr_idx);
733 }
734 }

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759 }
760
761 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): "
762 "register %s value %#x\n", miscRegName[misc_reg], value);
763 return value;
764}
765
766void
727 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
728
729 if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
730 ((lr & ICH_LR_EL2_HW) != 0 ||
731 (lr & ICH_LR_EL2_EOI) == 0)) {
732 value |= (1 << lr_idx);
733 }
734 }

--- 24 unchanged lines hidden (view full) ---

759 }
760
761 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): "
762 "register %s value %#x\n", miscRegName[misc_reg], value);
763 return value;
764}
765
766void
767Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
767Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
768{
769 bool do_virtual_update = false;
770 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): "
771 "register %s value %#x\n", miscRegName[misc_reg], val);
772 bool hcr_fmo = getHCREL2FMO();
773 bool hcr_imo = getHCREL2IMO();
774
775 switch (misc_reg) {

--- 83 unchanged lines hidden (view full) ---

859 }
860
861 int lr_idx = virtualFindActive(int_id);
862
863 if (lr_idx < 0) {
864 // No LR found matching
865 virtualIncrementEOICount();
866 } else {
768{
769 bool do_virtual_update = false;
770 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): "
771 "register %s value %#x\n", miscRegName[misc_reg], val);
772 bool hcr_fmo = getHCREL2FMO();
773 bool hcr_imo = getHCREL2IMO();
774
775 switch (misc_reg) {

--- 83 unchanged lines hidden (view full) ---

859 }
860
861 int lr_idx = virtualFindActive(int_id);
862
863 if (lr_idx < 0) {
864 // No LR found matching
865 virtualIncrementEOICount();
866 } else {
867 ArmISA::MiscReg lr =
867 RegVal lr =
868 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
869 Gicv3::GroupId lr_group =
870 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
871 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
872
873 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
874 //JAIRO if (!virtualIsEOISplitMode())
875 {

--- 60 unchanged lines hidden (view full) ---

936 }
937
938 int lr_idx = virtualFindActive(int_id);
939
940 if (lr_idx < 0) {
941 // No LR found matching
942 virtualIncrementEOICount();
943 } else {
868 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
869 Gicv3::GroupId lr_group =
870 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
871 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
872
873 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
874 //JAIRO if (!virtualIsEOISplitMode())
875 {

--- 60 unchanged lines hidden (view full) ---

936 }
937
938 int lr_idx = virtualFindActive(int_id);
939
940 if (lr_idx < 0) {
941 // No LR found matching
942 virtualIncrementEOICount();
943 } else {
944 ArmISA::MiscReg lr =
944 RegVal lr =
945 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
946 Gicv3::GroupId lr_group =
947 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
948 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
949
950 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
951 if (!virtualIsEOISplitMode()) {
952 virtualDeactivateIRQ(lr_idx);

--- 157 unchanged lines hidden (view full) ---

1110
1111 break;
1112 }
1113
1114 case MISCREG_ICV_BPR0_EL1:
1115 case MISCREG_ICV_BPR1_EL1: {
1116 Gicv3::GroupId group =
1117 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
945 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
946 Gicv3::GroupId lr_group =
947 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
948 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
949
950 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) {
951 if (!virtualIsEOISplitMode()) {
952 virtualDeactivateIRQ(lr_idx);

--- 157 unchanged lines hidden (view full) ---

1110
1111 break;
1112 }
1113
1114 case MISCREG_ICV_BPR0_EL1:
1115 case MISCREG_ICV_BPR1_EL1: {
1116 Gicv3::GroupId group =
1117 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1118 ArmISA::MiscReg ich_vmcr_el2 =
1118 RegVal ich_vmcr_el2 =
1119 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1120
1121 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
1122 // reads return bpr0 + 1 saturated to 7, writes ignored
1123 return;
1124 }
1125
1126 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;

--- 44 unchanged lines hidden (view full) ---

1171 mask = ICC_CTLR_EL1_EOIMODE;
1172 } else if (haveEL(EL3) and distributor->DS == 1) {
1173 mask = ICC_CTLR_EL1_PMHE | ICC_CTLR_EL1_CBPR |
1174 ICC_CTLR_EL1_EOIMODE;
1175 } else {
1176 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
1177 }
1178
1119 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1120
1121 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
1122 // reads return bpr0 + 1 saturated to 7, writes ignored
1123 return;
1124 }
1125
1126 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS;

--- 44 unchanged lines hidden (view full) ---

1171 mask = ICC_CTLR_EL1_EOIMODE;
1172 } else if (haveEL(EL3) and distributor->DS == 1) {
1173 mask = ICC_CTLR_EL1_PMHE | ICC_CTLR_EL1_CBPR |
1174 ICC_CTLR_EL1_EOIMODE;
1175 } else {
1176 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
1177 }
1178
1179 ArmISA::MiscReg old_val =
1179 RegVal old_val =
1180 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1181 old_val &= ~mask;
1182 val = old_val | (val & mask);
1183 break;
1184 }
1185
1186 case MISCREG_ICV_CTLR_EL1: {
1180 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1181 old_val &= ~mask;
1182 val = old_val | (val & mask);
1183 break;
1184 }
1185
1186 case MISCREG_ICV_CTLR_EL1: {
1187 ArmISA::MiscReg ich_vmcr_el2 =
1187 RegVal ich_vmcr_el2 =
1188 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1189 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
1190 val & ICC_CTLR_EL1_CBPR ? 1 : 0);
1191 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
1192 val & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
1193 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1194 do_virtual_update = true;
1195 break;
1196 }
1197
1198 case MISCREG_ICC_MCTLR:
1199 case MISCREG_ICC_CTLR_EL3: {
1188 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1189 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
1190 val & ICC_CTLR_EL1_CBPR ? 1 : 0);
1191 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
1192 val & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
1193 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1194 do_virtual_update = true;
1195 break;
1196 }
1197
1198 case MISCREG_ICC_MCTLR:
1199 case MISCREG_ICC_CTLR_EL3: {
1200 ArmISA::MiscReg icc_ctlr_el1_s =
1200 RegVal icc_ctlr_el1_s =
1201 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1201 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1202 ArmISA::MiscReg icc_ctlr_el1_ns =
1202 RegVal icc_ctlr_el1_ns =
1203 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1204
1205 // ICC_CTLR_EL1(NS).EOImode is an alias of
1206 // ICC_CTLR_EL3.EOImode_EL1NS
1207 if (val & ICC_CTLR_EL3_EOIMODE_EL1NS) {
1208 icc_ctlr_el1_ns |= ICC_CTLR_EL1_EOIMODE;
1209 } else {
1210 icc_ctlr_el1_ns &= ~ICC_CTLR_EL1_EOIMODE;

--- 18 unchanged lines hidden (view full) ---

1229 icc_ctlr_el1_s |= ICC_CTLR_EL1_CBPR;
1230 } else {
1231 icc_ctlr_el1_s &= ~ICC_CTLR_EL1_CBPR;
1232 }
1233
1234 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1235 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, icc_ctlr_el1_ns);
1236 // Only ICC_CTLR_EL3_EOIMODE_EL3 is writable
1203 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
1204
1205 // ICC_CTLR_EL1(NS).EOImode is an alias of
1206 // ICC_CTLR_EL3.EOImode_EL1NS
1207 if (val & ICC_CTLR_EL3_EOIMODE_EL1NS) {
1208 icc_ctlr_el1_ns |= ICC_CTLR_EL1_EOIMODE;
1209 } else {
1210 icc_ctlr_el1_ns &= ~ICC_CTLR_EL1_EOIMODE;

--- 18 unchanged lines hidden (view full) ---

1229 icc_ctlr_el1_s |= ICC_CTLR_EL1_CBPR;
1230 } else {
1231 icc_ctlr_el1_s &= ~ICC_CTLR_EL1_CBPR;
1232 }
1233
1234 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1235 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, icc_ctlr_el1_ns);
1236 // Only ICC_CTLR_EL3_EOIMODE_EL3 is writable
1237 ArmISA::MiscReg old_icc_ctlr_el3 =
1237 RegVal old_icc_ctlr_el3 =
1238 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1239 old_icc_ctlr_el3 &= ~(ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM);
1240 val = old_icc_ctlr_el3 |
1241 (val & (ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM));
1242 break;
1243 }
1244
1245 case MISCREG_ICC_PMR:

--- 6 unchanged lines hidden (view full) ---

1252 val &= 0xff;
1253 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1254
1255 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1256 /*
1257 * NS access and Group 0 is inaccessible to NS: return the
1258 * NS view of the current priority
1259 */
1238 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
1239 old_icc_ctlr_el3 &= ~(ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM);
1240 val = old_icc_ctlr_el3 |
1241 (val & (ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM));
1242 break;
1243 }
1244
1245 case MISCREG_ICC_PMR:

--- 6 unchanged lines hidden (view full) ---

1252 val &= 0xff;
1253 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1254
1255 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
1256 /*
1257 * NS access and Group 0 is inaccessible to NS: return the
1258 * NS view of the current priority
1259 */
1260 ArmISA::MiscReg old_icc_pmr_el1 =
1260 RegVal old_icc_pmr_el1 =
1261 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1262
1263 if (!(old_icc_pmr_el1 & 0x80)) {
1264 /* Current PMR in the secure range, don't allow NS to
1265 * change it */
1266 return;
1267 }
1268

--- 10 unchanged lines hidden (view full) ---

1279 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1280 }
1281
1282 break;
1283 }
1284
1285 case MISCREG_ICV_IGRPEN0_EL1: {
1286 bool enable = val & 0x1;
1261 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
1262
1263 if (!(old_icc_pmr_el1 & 0x80)) {
1264 /* Current PMR in the secure range, don't allow NS to
1265 * change it */
1266 return;
1267 }
1268

--- 10 unchanged lines hidden (view full) ---

1279 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1280 }
1281
1282 break;
1283 }
1284
1285 case MISCREG_ICV_IGRPEN0_EL1: {
1286 bool enable = val & 0x1;
1287 ArmISA::MiscReg ich_vmcr_el2 =
1287 RegVal ich_vmcr_el2 =
1288 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1289 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1290 ICH_VMCR_EL2_VENG0_SHIFT, enable);
1291 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1292 virtualUpdate();
1293 return;
1294 }
1295
1296 case MISCREG_ICC_IGRPEN1:
1297 case MISCREG_ICC_IGRPEN1_EL1: { // Interrupt Group 1 Enable Register
1298 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1299 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1300 }
1301
1302 break;
1303 }
1304
1305 case MISCREG_ICV_IGRPEN1_EL1: {
1306 bool enable = val & 0x1;
1288 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1289 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1290 ICH_VMCR_EL2_VENG0_SHIFT, enable);
1291 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1292 virtualUpdate();
1293 return;
1294 }
1295
1296 case MISCREG_ICC_IGRPEN1:
1297 case MISCREG_ICC_IGRPEN1_EL1: { // Interrupt Group 1 Enable Register
1298 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
1299 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1300 }
1301
1302 break;
1303 }
1304
1305 case MISCREG_ICV_IGRPEN1_EL1: {
1306 bool enable = val & 0x1;
1307 ArmISA::MiscReg ich_vmcr_el2 =
1307 RegVal ich_vmcr_el2 =
1308 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1309 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1310 ICH_VMCR_EL2_VENG1_SHIFT, enable);
1311 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1312 virtualUpdate();
1313 return;
1314 }
1315

--- 86 unchanged lines hidden (view full) ---

1402 bool dib = val & ICC_SRE_EL1_DIB;
1403
1404 if (haveEL(EL3) && !distributor->DS) {
1405 // DIB is RO alias of ICC_SRE_EL3.DIB
1406 // DFB is RO alias of ICC_SRE_EL3.DFB
1407 } else if (haveEL(EL3) && distributor->DS) {
1408 // DIB is RW alias of ICC_SRE_EL3.DIB
1409 // DFB is RW alias of ICC_SRE_EL3.DFB
1308 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1309 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1310 ICH_VMCR_EL2_VENG1_SHIFT, enable);
1311 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1312 virtualUpdate();
1313 return;
1314 }
1315

--- 86 unchanged lines hidden (view full) ---

1402 bool dib = val & ICC_SRE_EL1_DIB;
1403
1404 if (haveEL(EL3) && !distributor->DS) {
1405 // DIB is RO alias of ICC_SRE_EL3.DIB
1406 // DFB is RO alias of ICC_SRE_EL3.DFB
1407 } else if (haveEL(EL3) && distributor->DS) {
1408 // DIB is RW alias of ICC_SRE_EL3.DIB
1409 // DFB is RW alias of ICC_SRE_EL3.DFB
1410 ArmISA::MiscReg icc_sre_el3 =
1410 RegVal icc_sre_el3 =
1411 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
1412 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DFB, dfb);
1413 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DIB, dib);
1414 isa->setMiscRegNoEffect(MISCREG_ICC_SRE_EL3, icc_sre_el3);
1415 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
1416 // DIB is RO alias of ICC_SRE_EL2.DIB
1417 // DFB is RO alias of ICC_SRE_EL2.DFB
1418 } else {

--- 27 unchanged lines hidden (view full) ---

1446 break;
1447
1448 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
1449 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1450 {
1451 // Enforce RES0 bits in priority field, 5 of 8 bits used
1452 val = insertBits(val, ICH_LRC_PRIORITY_SHIFT + 2,
1453 ICH_LRC_PRIORITY_SHIFT, 0);
1411 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
1412 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DFB, dfb);
1413 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DIB, dib);
1414 isa->setMiscRegNoEffect(MISCREG_ICC_SRE_EL3, icc_sre_el3);
1415 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
1416 // DIB is RO alias of ICC_SRE_EL2.DIB
1417 // DFB is RO alias of ICC_SRE_EL2.DFB
1418 } else {

--- 27 unchanged lines hidden (view full) ---

1446 break;
1447
1448 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
1449 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
1450 {
1451 // Enforce RES0 bits in priority field, 5 of 8 bits used
1452 val = insertBits(val, ICH_LRC_PRIORITY_SHIFT + 2,
1453 ICH_LRC_PRIORITY_SHIFT, 0);
1454 ArmISA::MiscReg old_val = isa->readMiscRegNoEffect(misc_reg);
1454 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1455 val = (old_val & 0xffffffff) | (val << 32);
1456 do_virtual_update = true;
1457 break;
1458 }
1459
1460 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1461 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1455 val = (old_val & 0xffffffff) | (val << 32);
1456 do_virtual_update = true;
1457 break;
1458 }
1459
1460 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
1461 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
1462 ArmISA::MiscReg old_val = isa->readMiscRegNoEffect(misc_reg);
1462 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1463 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1464 do_virtual_update = true;
1465 break;
1466 }
1467
1468 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1469 // Enforce RES0 bits in priority field, 5 of 8 bits used
1470 val = insertBits(val, ICH_LR_EL2_PRIORITY_SHIFT + 2,

--- 41 unchanged lines hidden (view full) ---

1512 virtualUpdate();
1513 }
1514}
1515
1516int
1517Gicv3CPUInterface::virtualFindActive(uint32_t int_id)
1518{
1519 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1463 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1464 do_virtual_update = true;
1465 break;
1466 }
1467
1468 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1469 // Enforce RES0 bits in priority field, 5 of 8 bits used
1470 val = insertBits(val, ICH_LR_EL2_PRIORITY_SHIFT + 2,

--- 41 unchanged lines hidden (view full) ---

1512 virtualUpdate();
1513 }
1514}
1515
1516int
1517Gicv3CPUInterface::virtualFindActive(uint32_t int_id)
1518{
1519 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
1520 ArmISA::MiscReg lr =
1520 RegVal lr =
1521 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1522 uint32_t lr_intid = bits(lr, 31, 0);
1523
1524 if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && lr_intid == int_id) {
1525 return lr_idx;
1526 }
1527 }
1528

--- 63 unchanged lines hidden (view full) ---

1592
1593 return hppi.intid;
1594}
1595
1596void
1597Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1598{
1599 int apr_misc_reg;
1521 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1522 uint32_t lr_intid = bits(lr, 31, 0);
1523
1524 if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && lr_intid == int_id) {
1525 return lr_idx;
1526 }
1527 }
1528

--- 63 unchanged lines hidden (view full) ---

1592
1593 return hppi.intid;
1594}
1595
1596void
1597Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
1598{
1599 int apr_misc_reg;
1600 ArmISA::MiscReg apr;
1600 RegVal apr;
1601 apr_misc_reg = group == Gicv3::G0S ?
1602 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1603 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1604
1605 if (apr) {
1606 /* Clear the lowest set bit */
1607 apr &= apr - 1;
1608 isa->setMiscRegNoEffect(apr_misc_reg, apr);

--- 11 unchanged lines hidden (view full) ---

1620 * Return the priority value for the bit we just cleared,
1621 * or 0xff if no bits were set in the AP registers at all.
1622 * Note that though the ich_apr[] are uint64_t only the low
1623 * 32 bits are actually relevant.
1624 */
1625 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1626
1627 for (int i = 0; i < apr_max; i++) {
1601 apr_misc_reg = group == Gicv3::G0S ?
1602 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1603 apr = isa->readMiscRegNoEffect(apr_misc_reg);
1604
1605 if (apr) {
1606 /* Clear the lowest set bit */
1607 apr &= apr - 1;
1608 isa->setMiscRegNoEffect(apr_misc_reg, apr);

--- 11 unchanged lines hidden (view full) ---

1620 * Return the priority value for the bit we just cleared,
1621 * or 0xff if no bits were set in the AP registers at all.
1622 * Note that though the ich_apr[] are uint64_t only the low
1623 * 32 bits are actually relevant.
1624 */
1625 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
1626
1627 for (int i = 0; i < apr_max; i++) {
1628 ArmISA::MiscReg vapr0 =
1629 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1630 ArmISA::MiscReg vapr1 =
1631 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1628 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1629 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
1632
1633 if (!vapr0 && !vapr1) {
1634 continue;
1635 }
1636
1637 int vapr0_count = ctz32(vapr0);
1638 int vapr1_count = ctz32(vapr1);
1639

--- 17 unchanged lines hidden (view full) ---

1657Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1658{
1659 // Update active priority registers.
1660 uint32_t prio = hppi.prio & 0xf8;
1661 int apr_bit = prio >> (8 - PRIORITY_BITS);
1662 int reg_bit = apr_bit % 32;
1663 int apr_idx = group == Gicv3::G0S ?
1664 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1630
1631 if (!vapr0 && !vapr1) {
1632 continue;
1633 }
1634
1635 int vapr0_count = ctz32(vapr0);
1636 int vapr1_count = ctz32(vapr1);
1637

--- 17 unchanged lines hidden (view full) ---

1655Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
1656{
1657 // Update active priority registers.
1658 uint32_t prio = hppi.prio & 0xf8;
1659 int apr_bit = prio >> (8 - PRIORITY_BITS);
1660 int reg_bit = apr_bit % 32;
1661 int apr_idx = group == Gicv3::G0S ?
1662 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
1665 ArmISA::MiscReg apr = isa->readMiscRegNoEffect(apr_idx);
1663 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1666 apr |= (1 << reg_bit);
1667 isa->setMiscRegNoEffect(apr_idx, apr);
1668
1669 // Move interrupt state from pending to active.
1670 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1671 // SGI or PPI, redistributor
1672 redistributor->activateIRQ(int_id);
1673 redistributor->updateAndInformCPUInterface();
1674 } else if (int_id < Gicv3::INTID_SECURE) {
1675 // SPI, distributor
1676 distributor->activateIRQ(int_id);
1677 distributor->updateAndInformCPUInterfaces();
1678 }
1679}
1680
1681void
1682Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1683{
1684 // Update active priority registers.
1664 apr |= (1 << reg_bit);
1665 isa->setMiscRegNoEffect(apr_idx, apr);
1666
1667 // Move interrupt state from pending to active.
1668 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
1669 // SGI or PPI, redistributor
1670 redistributor->activateIRQ(int_id);
1671 redistributor->updateAndInformCPUInterface();
1672 } else if (int_id < Gicv3::INTID_SECURE) {
1673 // SPI, distributor
1674 distributor->activateIRQ(int_id);
1675 distributor->updateAndInformCPUInterfaces();
1676 }
1677}
1678
1679void
1680Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
1681{
1682 // Update active priority registers.
1685 ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1683 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1686 lr_idx);
1687 Gicv3::GroupId group = lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
1688 uint8_t prio = bits(lr, 55, 48) & 0xf8;
1689 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1690 int reg_no = apr_bit / 32;
1691 int reg_bit = apr_bit % 32;
1692 int apr_idx = group == Gicv3::G0S ?
1693 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1684 lr_idx);
1685 Gicv3::GroupId group = lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
1686 uint8_t prio = bits(lr, 55, 48) & 0xf8;
1687 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS);
1688 int reg_no = apr_bit / 32;
1689 int reg_bit = apr_bit % 32;
1690 int apr_idx = group == Gicv3::G0S ?
1691 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
1694 ArmISA::MiscReg apr = isa->readMiscRegNoEffect(apr_idx);
1692 RegVal apr = isa->readMiscRegNoEffect(apr_idx);
1695 apr |= (1 << reg_bit);
1696 isa->setMiscRegNoEffect(apr_idx, apr);
1697 // Move interrupt state from pending to active.
1698 lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
1699 lr |= ICH_LR_EL2_STATE_ACTIVE_BIT;
1700 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, lr);
1701}
1702

--- 11 unchanged lines hidden (view full) ---

1714 } else {
1715 return;
1716 }
1717}
1718
1719void
1720Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1721{
1693 apr |= (1 << reg_bit);
1694 isa->setMiscRegNoEffect(apr_idx, apr);
1695 // Move interrupt state from pending to active.
1696 lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
1697 lr |= ICH_LR_EL2_STATE_ACTIVE_BIT;
1698 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, lr);
1699}
1700

--- 11 unchanged lines hidden (view full) ---

1712 } else {
1713 return;
1714 }
1715}
1716
1717void
1718Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
1719{
1722 ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1720 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1723 lr_idx);
1724
1725 if (lr & ICH_LR_EL2_HW) {
1726 // Deactivate the associated physical interrupt
1727 int pintid = bits(lr, 41, 32);
1728
1729 if (pintid < Gicv3::INTID_SECURE) {
1730 Gicv3::GroupId group =

--- 54 unchanged lines hidden (view full) ---

1785 }
1786
1787 return ~0U << (bpr + 1);
1788}
1789
1790uint32_t
1791Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group)
1792{
1721 lr_idx);
1722
1723 if (lr & ICH_LR_EL2_HW) {
1724 // Deactivate the associated physical interrupt
1725 int pintid = bits(lr, 41, 32);
1726
1727 if (pintid < Gicv3::INTID_SECURE) {
1728 Gicv3::GroupId group =

--- 54 unchanged lines hidden (view full) ---

1783 }
1784
1785 return ~0U << (bpr + 1);
1786}
1787
1788uint32_t
1789Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group)
1790{
1793 ArmISA::MiscReg ich_vmcr_el2 =
1791 RegVal ich_vmcr_el2 =
1794 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1795
1796 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
1797 group = Gicv3::G0S;
1798 }
1799
1800 int bpr;
1801

--- 21 unchanged lines hidden (view full) ---

1823 return isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1) &
1824 ICC_CTLR_EL1_EOIMODE;
1825 }
1826}
1827
1828bool
1829Gicv3CPUInterface::virtualIsEOISplitMode()
1830{
1792 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1793
1794 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
1795 group = Gicv3::G0S;
1796 }
1797
1798 int bpr;
1799

--- 21 unchanged lines hidden (view full) ---

1821 return isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1) &
1822 ICC_CTLR_EL1_EOIMODE;
1823 }
1824}
1825
1826bool
1827Gicv3CPUInterface::virtualIsEOISplitMode()
1828{
1831 ArmISA::MiscReg ich_vmcr_el2 =
1832 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1829 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1833 return ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
1834}
1835
1836int
1837Gicv3CPUInterface::highestActiveGroup()
1838{
1839 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1840 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));

--- 51 unchanged lines hidden (view full) ---

1892void
1893Gicv3CPUInterface::virtualUpdate()
1894{
1895 bool signal_IRQ = false;
1896 bool signal_FIQ = false;
1897 int lr_idx = getHPPVILR();
1898
1899 if (lr_idx >= 0) {
1830 return ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
1831}
1832
1833int
1834Gicv3CPUInterface::highestActiveGroup()
1835{
1836 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
1837 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));

--- 51 unchanged lines hidden (view full) ---

1889void
1890Gicv3CPUInterface::virtualUpdate()
1891{
1892 bool signal_IRQ = false;
1893 bool signal_FIQ = false;
1894 int lr_idx = getHPPVILR();
1895
1896 if (lr_idx >= 0) {
1900 ArmISA::MiscReg ich_lr_el2 =
1897 RegVal ich_lr_el2 =
1901 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1902
1903 if (hppviCanPreempt(lr_idx)) {
1904 if (ich_lr_el2 & ICH_LR_EL2_GROUP) {
1905 signal_IRQ = true;
1906 } else {
1907 signal_FIQ = true;
1908 }
1909 }
1910 }
1911
1898 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1899
1900 if (hppviCanPreempt(lr_idx)) {
1901 if (ich_lr_el2 & ICH_LR_EL2_GROUP) {
1902 signal_IRQ = true;
1903 } else {
1904 signal_FIQ = true;
1905 }
1906 }
1907 }
1908
1912 ArmISA::MiscReg ich_hcr_el2 =
1913 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1909 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
1914
1915 if (ich_hcr_el2 & ICH_HCR_EL2_EN) {
1916 if (maintenanceInterruptStatus()) {
1917 redistributor->sendPPInt(25);
1918 }
1919 }
1920
1921 if (signal_IRQ) {

--- 13 unchanged lines hidden (view full) ---

1935 }
1936}
1937
1938// Returns the intex of the LR with the HPPI
1939int
1940Gicv3CPUInterface::getHPPVILR()
1941{
1942 int idx = -1;
1910
1911 if (ich_hcr_el2 & ICH_HCR_EL2_EN) {
1912 if (maintenanceInterruptStatus()) {
1913 redistributor->sendPPInt(25);
1914 }
1915 }
1916
1917 if (signal_IRQ) {

--- 13 unchanged lines hidden (view full) ---

1931 }
1932}
1933
1934// Returns the intex of the LR with the HPPI
1935int
1936Gicv3CPUInterface::getHPPVILR()
1937{
1938 int idx = -1;
1943 ArmISA::MiscReg ich_vmcr_el2 =
1944 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1939 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1945
1946 if (!(ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
1947 // VG0 and VG1 disabled...
1948 return idx;
1949 }
1950
1951 uint8_t highest_prio = 0xff;
1952
1953 for (int i = 0; i < 16; i++) {
1940
1941 if (!(ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
1942 // VG0 and VG1 disabled...
1943 return idx;
1944 }
1945
1946 uint8_t highest_prio = 0xff;
1947
1948 for (int i = 0; i < 16; i++) {
1954 ArmISA::MiscReg ich_lri_el2 =
1949 RegVal ich_lri_el2 =
1955 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
1956 uint8_t state = bits(ich_lri_el2, 63, 62);
1957
1958 if (state != Gicv3::INT_PENDING) {
1959 continue;
1960 }
1961
1962 if (ich_lri_el2 & ICH_LR_EL2_GROUP) {

--- 17 unchanged lines hidden (view full) ---

1980 }
1981
1982 return idx;
1983}
1984
1985bool
1986Gicv3CPUInterface::hppviCanPreempt(int lr_idx)
1987{
1950 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
1951 uint8_t state = bits(ich_lri_el2, 63, 62);
1952
1953 if (state != Gicv3::INT_PENDING) {
1954 continue;
1955 }
1956
1957 if (ich_lri_el2 & ICH_LR_EL2_GROUP) {

--- 17 unchanged lines hidden (view full) ---

1975 }
1976
1977 return idx;
1978}
1979
1980bool
1981Gicv3CPUInterface::hppviCanPreempt(int lr_idx)
1982{
1988 ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1989 lr_idx);
1983 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1990
1991 if (!(isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2) & ICH_HCR_EL2_EN)) {
1992 // virtual interface is disabled
1993 return false;
1994 }
1995
1996 uint8_t prio = bits(lr, 55, 48);
1997 uint8_t vpmr =

--- 21 unchanged lines hidden (view full) ---

2019}
2020
2021uint8_t
2022Gicv3CPUInterface::virtualHighestActivePriority()
2023{
2024 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2025
2026 for (int i = 0; i < num_aprs; i++) {
1984
1985 if (!(isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2) & ICH_HCR_EL2_EN)) {
1986 // virtual interface is disabled
1987 return false;
1988 }
1989
1990 uint8_t prio = bits(lr, 55, 48);
1991 uint8_t vpmr =

--- 21 unchanged lines hidden (view full) ---

2013}
2014
2015uint8_t
2016Gicv3CPUInterface::virtualHighestActivePriority()
2017{
2018 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
2019
2020 for (int i = 0; i < num_aprs; i++) {
2027 ArmISA::MiscReg vapr =
2021 RegVal vapr =
2028 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2029 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2030
2031 if (!vapr) {
2032 continue;
2033 }
2034
2035 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2036 }
2037
2038 // no active interrups, return idle priority
2039 return 0xff;
2040}
2041
2042void
2043Gicv3CPUInterface::virtualIncrementEOICount()
2044{
2045 // Increment the EOICOUNT field in ICH_HCR_EL2
2022 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
2023 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
2024
2025 if (!vapr) {
2026 continue;
2027 }
2028
2029 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1);
2030 }
2031
2032 // no active interrups, return idle priority
2033 return 0xff;
2034}
2035
2036void
2037Gicv3CPUInterface::virtualIncrementEOICount()
2038{
2039 // Increment the EOICOUNT field in ICH_HCR_EL2
2046 ArmISA::MiscReg ich_hcr_el2 =
2047 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2040 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2048 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2049 EOI_cout++;
2050 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2051 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2052}
2053
2054/*
2055 * Should we signal the interrupt as IRQ or FIQ?

--- 205 unchanged lines hidden (view full) ---

2261 * If misr is not NULL then we should also collect the information
2262 * about the MISR.EOI, MISR.NP and MISR.U bits.
2263 */
2264 uint32_t value = 0;
2265 int valid_count = 0;
2266 bool seen_pending = false;
2267
2268 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2041 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2042 EOI_cout++;
2043 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
2044 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
2045}
2046
2047/*
2048 * Should we signal the interrupt as IRQ or FIQ?

--- 205 unchanged lines hidden (view full) ---

2254 * If misr is not NULL then we should also collect the information
2255 * about the MISR.EOI, MISR.NP and MISR.U bits.
2256 */
2257 uint32_t value = 0;
2258 int valid_count = 0;
2259 bool seen_pending = false;
2260
2261 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
2269 ArmISA::MiscReg lr =
2270 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2262 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2271
2272 if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) ==
2273 ICH_LR_EL2_EOI) {
2274 value |= (1 << lr_idx);
2275 }
2276
2277 if ((lr & ICH_LR_EL2_STATE_MASK)) {
2278 valid_count++;
2279 }
2280
2281 if (bits(lr, ICH_LR_EL2_STATE_SHIFT + ICH_LR_EL2_STATE_LENGTH,
2282 ICH_LR_EL2_STATE_SHIFT) == ICH_LR_EL2_STATE_PENDING) {
2283 seen_pending = true;
2284 }
2285 }
2286
2287 if (misr) {
2263
2264 if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) ==
2265 ICH_LR_EL2_EOI) {
2266 value |= (1 << lr_idx);
2267 }
2268
2269 if ((lr & ICH_LR_EL2_STATE_MASK)) {
2270 valid_count++;
2271 }
2272
2273 if (bits(lr, ICH_LR_EL2_STATE_SHIFT + ICH_LR_EL2_STATE_LENGTH,
2274 ICH_LR_EL2_STATE_SHIFT) == ICH_LR_EL2_STATE_PENDING) {
2275 seen_pending = true;
2276 }
2277 }
2278
2279 if (misr) {
2288 ArmISA::MiscReg ich_hcr_el2 =
2280 RegVal ich_hcr_el2 =
2289 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2290
2291 if (valid_count < 2 && (ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
2292 *misr |= ICH_MISR_EL2_U;
2293 }
2294
2295 if (!seen_pending && (ich_hcr_el2 & ICH_HCR_EL2_NPIE)) {
2296 *misr |= ICH_MISR_EL2_NP;

--- 11 unchanged lines hidden (view full) ---

2308Gicv3CPUInterface::maintenanceInterruptStatus()
2309{
2310 /* Return a set of bits indicating the maintenance interrupt status
2311 * (as seen in the ICH_MISR_EL2 register).
2312 */
2313 uint32_t value = 0;
2314 /* Scan list registers and fill in the U, NP and EOI bits */
2315 eoiMaintenanceInterruptStatus(&value);
2281 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2282
2283 if (valid_count < 2 && (ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
2284 *misr |= ICH_MISR_EL2_U;
2285 }
2286
2287 if (!seen_pending && (ich_hcr_el2 & ICH_HCR_EL2_NPIE)) {
2288 *misr |= ICH_MISR_EL2_NP;

--- 11 unchanged lines hidden (view full) ---

2300Gicv3CPUInterface::maintenanceInterruptStatus()
2301{
2302 /* Return a set of bits indicating the maintenance interrupt status
2303 * (as seen in the ICH_MISR_EL2 register).
2304 */
2305 uint32_t value = 0;
2306 /* Scan list registers and fill in the U, NP and EOI bits */
2307 eoiMaintenanceInterruptStatus(&value);
2316 ArmISA::MiscReg ich_hcr_el2 =
2317 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2318 ArmISA::MiscReg ich_vmcr_el2 =
2319 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2308 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2309 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
2320
2321 if (ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
2322 value |= ICH_MISR_EL2_LRENP;
2323 }
2324
2325 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
2326 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
2327 value |= ICH_MISR_EL2_VGRP0E;

--- 35 unchanged lines hidden --- 		2310
2311 if (ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
2312 value |= ICH_MISR_EL2_LRENP;
2313 }
2314
2315 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
2316 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
2317 value |= ICH_MISR_EL2_VGRP0E;

--- 35 unchanged lines hidden ---