1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Jairo Balart 29 */ 30 31#include "dev/arm/gic_v3_cpu_interface.hh" 32 33#include "arch/arm/isa.hh" 34#include "debug/GIC.hh" 35#include "dev/arm/gic_v3.hh" 36#include "dev/arm/gic_v3_distributor.hh" 37#include "dev/arm/gic_v3_redistributor.hh" 38 39Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 40 : BaseISADevice(), 41 gic(gic), 42 redistributor(nullptr), 43 distributor(nullptr), 44 cpuId(cpu_id) 45{ 46} 47
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48Gicv3CPUInterface::~Gicv3CPUInterface()
49{
50}
51
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48void 49Gicv3CPUInterface::init() 50{ 51 redistributor = gic->getRedistributor(cpuId); 52 distributor = gic->getDistributor(); 53} 54 55void 56Gicv3CPUInterface::initState() 57{ 58 reset(); 59} 60 61void 62Gicv3CPUInterface::reset() 63{ 64 hppi.prio = 0xff; 65} 66 67bool
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72Gicv3CPUInterface::getHCREL2FMO()
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68Gicv3CPUInterface::getHCREL2FMO() const |
69{ 70 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 71 72 if (hcr.tge && hcr.e2h) { 73 return false; 74 } else if (hcr.tge) { 75 return true; 76 } else { 77 return hcr.fmo; 78 } 79} 80 81bool
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86Gicv3CPUInterface::getHCREL2IMO()
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82Gicv3CPUInterface::getHCREL2IMO() const |
83{ 84 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 85 86 if (hcr.tge && hcr.e2h) { 87 return false; 88 } else if (hcr.tge) { 89 return true; 90 } else { 91 return hcr.imo; 92 } 93} 94 95RegVal 96Gicv3CPUInterface::readMiscReg(int misc_reg) 97{ 98 RegVal value = isa->readMiscRegNoEffect(misc_reg); 99 bool hcr_fmo = getHCREL2FMO(); 100 bool hcr_imo = getHCREL2IMO(); 101 102 switch (misc_reg) {
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103 // Active Priorities Group 1 Registers |
104 case MISCREG_ICC_AP1R0: 105 case MISCREG_ICC_AP1R0_EL1: { 106 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 107 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 108 } 109 110 break; 111 } 112 113 case MISCREG_ICC_AP1R1: 114 case MISCREG_ICC_AP1R1_EL1: 115 116 // only implemented if supporting 6 or more bits of priority 117 case MISCREG_ICC_AP1R2: 118 case MISCREG_ICC_AP1R2_EL1: 119 120 // only implemented if supporting 7 or more bits of priority 121 case MISCREG_ICC_AP1R3: 122 case MISCREG_ICC_AP1R3_EL1: 123 // only implemented if supporting 7 or more bits of priority 124 return 0; 125
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126 // Active Priorities Group 0 Registers |
127 case MISCREG_ICC_AP0R0: 128 case MISCREG_ICC_AP0R0_EL1: { 129 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 130 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 131 } 132 133 break; 134 } 135 136 case MISCREG_ICC_AP0R1: 137 case MISCREG_ICC_AP0R1_EL1: 138 139 // only implemented if supporting 6 or more bits of priority 140 case MISCREG_ICC_AP0R2: 141 case MISCREG_ICC_AP0R2_EL1: 142 143 // only implemented if supporting 7 or more bits of priority 144 case MISCREG_ICC_AP0R3: 145 case MISCREG_ICC_AP0R3_EL1: 146 // only implemented if supporting 7 or more bits of priority 147 return 0; 148
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149 // Interrupt Group 0 Enable register EL1 |
150 case MISCREG_ICC_IGRPEN0: 151 case MISCREG_ICC_IGRPEN0_EL1: { 152 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
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154 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
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153 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1); |
154 } 155 156 break; 157 } 158
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160 case MISCREG_ICV_IGRPEN0_EL1: {
161 RegVal ich_vmcr_el2 =
162 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
163 value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG0_SHIFT);
164 break;
165 }
166
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159 // Interrupt Group 1 Enable register EL1 |
160 case MISCREG_ICC_IGRPEN1: 161 case MISCREG_ICC_IGRPEN1_EL1: { 162 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
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170 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
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163 return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1); |
164 } 165 166 break; 167 } 168
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176 case MISCREG_ICV_IGRPEN1_EL1: {
177 RegVal ich_vmcr_el2 =
178 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
179 value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG1_SHIFT);
180 break;
181 }
182
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169 // Interrupt Group 1 Enable register EL3 |
170 case MISCREG_ICC_MGRPEN1:
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184 case MISCREG_ICC_IGRPEN1_EL3: {
185 // EnableGrp1S and EnableGrp1NS are aliased with
186 // ICC_IGRPEN1_EL1_S.Enable and ICC_IGRPEN1_EL1_NS.Enable
187 bool enable_grp_1s =
188 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S) &
189 ICC_IGRPEN1_EL1_ENABLE;
190 bool enable_grp_1ns =
191 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS) &
192 ICC_IGRPEN1_EL1_ENABLE;
193 value = 0;
194
195 if (enable_grp_1s) {
196 value |= ICC_IGRPEN1_EL3_ENABLEGRP1S;
197 }
198
199 if (enable_grp_1ns) {
200 value |= ICC_IGRPEN1_EL3_ENABLEGRP1NS;
201 }
202
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171 case MISCREG_ICC_IGRPEN1_EL3: |
172 break;
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204 }
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173
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174 // Running Priority Register |
175 case MISCREG_ICC_RPR: 176 case MISCREG_ICC_RPR_EL1: { 177 if ((currEL() == EL1) && !inSecureState() &&
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209 (hcr_imo || hcr_fmo)) {
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178 (hcr_imo || hcr_fmo)) { |
179 return readMiscReg(MISCREG_ICV_RPR_EL1); 180 } 181 182 uint8_t rprio = highestActivePriority(); 183 184 if (haveEL(EL3) && !inSecureState() &&
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216 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
217 /* NS GIC access and Group 0 is inaccessible to NS */
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185 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 186 // Spec section 4.8.1 187 // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 |
188 if ((rprio & 0x80) == 0) {
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219 /* NS should not see priorities in the Secure half of the
220 * range */
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189 // If the current priority mask value is in the range of 190 // 0x00-0x7F a read access returns the value 0x0 |
191 rprio = 0; 192 } else if (rprio != 0xff) {
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223 /* Non-idle priority: show the Non-secure view of it */
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193 // If the current priority mask value is in the range of 194 // 0x80-0xFF a read access returns the Non-secure read of 195 // the current value |
196 rprio = (rprio << 1) & 0xff; 197 } 198 } 199 200 value = rprio; 201 break; 202 } 203
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204 // Virtual Running Priority Register |
205 case MISCREG_ICV_RPR_EL1: { 206 value = virtualHighestActivePriority(); 207 break; 208 } 209
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210 // Highest Priority Pending Interrupt Register 0 |
211 case MISCREG_ICC_HPPIR0: 212 case MISCREG_ICC_HPPIR0_EL1: { 213 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 214 return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 215 } 216 217 value = getHPPIR0(); 218 break; 219 } 220
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221 // Virtual Highest Priority Pending Interrupt Register 0 |
222 case MISCREG_ICV_HPPIR0_EL1: { 223 value = Gicv3::INTID_SPURIOUS; 224 int lr_idx = getHPPVILR(); 225 226 if (lr_idx >= 0) {
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252 RegVal lr =
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227 ICH_LR_EL2 ich_lr_el2 = |
228 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 229 Gicv3::GroupId group =
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255 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
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230 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; |
231 232 if (group == Gicv3::G0S) {
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258 value = bits(lr, 31, 0);
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233 value = ich_lr_el2.vINTID; |
234 } 235 } 236 237 break; 238 } 239
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240 // Highest Priority Pending Interrupt Register 1 |
241 case MISCREG_ICC_HPPIR1: 242 case MISCREG_ICC_HPPIR1_EL1: { 243 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 244 return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 245 } 246 247 value = getHPPIR1(); 248 break; 249 } 250
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251 // Virtual Highest Priority Pending Interrupt Register 1 |
252 case MISCREG_ICV_HPPIR1_EL1: { 253 value = Gicv3::INTID_SPURIOUS; 254 int lr_idx = getHPPVILR(); 255 256 if (lr_idx >= 0) {
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280 RegVal lr =
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257 ICH_LR_EL2 ich_lr_el2 = |
258 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 259 Gicv3::GroupId group =
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283 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
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260 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; |
261 262 if (group == Gicv3::G1NS) {
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286 value = bits(lr, 31, 0);
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263 value = ich_lr_el2.vINTID; |
264 } 265 } 266 267 break; 268 } 269
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270 // Binary Point Register 0 |
271 case MISCREG_ICC_BPR0: 272 case MISCREG_ICC_BPR0_EL1: 273 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 274 return readMiscReg(MISCREG_ICV_BPR0_EL1); 275 } 276 277 M5_FALLTHROUGH; 278
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279 // Binary Point Register 1 |
280 case MISCREG_ICC_BPR1:
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302 case MISCREG_ICC_BPR1_EL1:
303 if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
304 return readMiscReg(MISCREG_ICV_BPR1_EL1);
305 }
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281 case MISCREG_ICC_BPR1_EL1: { 282 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 283 return readMiscReg(MISCREG_ICV_BPR1_EL1); 284 } |
285
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307 {
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286 Gicv3::GroupId group = 287 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 288 289 if (group == Gicv3::G1S && !inSecureState()) { 290 group = Gicv3::G1NS; 291 } 292
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315 if ((group == Gicv3::G1S) &&
316 !isEL3OrMon() &&
317 (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
318 & ICC_CTLR_EL1_CBPR)) {
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293 ICC_CTLR_EL1 icc_ctlr_el1_s = 294 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 295 296 if ((group == Gicv3::G1S) && !isEL3OrMon() && 297 icc_ctlr_el1_s.CBPR) { |
298 group = Gicv3::G0S; 299 } 300 301 bool sat_inc = false; 302
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324 if ((group == Gicv3::G1NS) &&
325 (currEL() < EL3) &&
326 (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
327 & ICC_CTLR_EL1_CBPR)) {
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303 ICC_CTLR_EL1 icc_ctlr_el1_ns = 304 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 305 306 if ((group == Gicv3::G1NS) && (currEL() < EL3) && 307 icc_ctlr_el1_ns.CBPR) { |
308 // Reads return BPR0 + 1 saturated to 7, WI 309 group = Gicv3::G0S; 310 sat_inc = true; 311 } 312 313 uint8_t bpr; 314 315 if (group == Gicv3::G0S) { 316 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 317 } else { 318 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1); 319 } 320 321 if (sat_inc) { 322 bpr++; 323 324 if (bpr > 7) { 325 bpr = 7; 326 } 327 } 328 329 value = bpr; 330 break;
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351 }
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331 } |
332
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333 // Virtual Binary Point Register 1 |
334 case MISCREG_ICV_BPR0_EL1: 335 case MISCREG_ICV_BPR1_EL1: { 336 Gicv3::GroupId group = 337 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
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357 RegVal ich_vmcr_el2 =
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338 ICH_VMCR_EL2 ich_vmcr_el2 = |
339 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 340 bool sat_inc = false; 341
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361 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
362 // reads return bpr0 + 1 saturated to 7, writes ignored
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342 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 343 // bpr0 + 1 saturated to 7, WI |
344 group = Gicv3::G0S; 345 sat_inc = true; 346 } 347 348 uint8_t vbpr; 349 350 if (group == Gicv3::G0S) {
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370 vbpr = bits(ich_vmcr_el2, 23, 21);
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351 vbpr = ich_vmcr_el2.VBPR0; |
352 } else {
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372 vbpr = bits(ich_vmcr_el2, 20, 18);
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353 vbpr = ich_vmcr_el2.VBPR1; |
354 } 355 356 if (sat_inc) { 357 vbpr++; 358 359 if (vbpr > 7) { 360 vbpr = 7; 361 } 362 } 363 364 value = vbpr; 365 break; 366 } 367
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368 // Interrupt Priority Mask Register |
369 case MISCREG_ICC_PMR:
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388 case MISCREG_ICC_PMR_EL1: // Priority Mask Register
389 if ((currEL() == EL1) && !inSecureState() &&
390 (hcr_imo || hcr_fmo)) {
391 return readMiscReg(MISCREG_ICV_PMR_EL1);
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370 case MISCREG_ICC_PMR_EL1: 371 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 372 return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1); |
373 } 374 375 if (haveEL(EL3) && !inSecureState() &&
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395 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
396 /* NS GIC access and Group 0 is inaccessible to NS */
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376 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 377 // Spec section 4.8.1 378 // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: |
379 if ((value & 0x80) == 0) {
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398 /* NS should not see priorities in the Secure half of the
399 * range */
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380 // If the current priority mask value is in the range of 381 // 0x00-0x7F a read access returns the value 0x00. |
382 value = 0; 383 } else if (value != 0xff) {
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402 /* Non-idle priority: show the Non-secure view of it */
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384 // If the current priority mask value is in the range of 385 // 0x80-0xFF a read access returns the Non-secure read of the 386 // current value. |
387 value = (value << 1) & 0xff; 388 } 389 } 390 391 break; 392
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409 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
410 RegVal ich_vmcr_el2 =
411 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
412
413 value = ich_vmcr_el2 >> ICH_VMCR_EL2_VPMR_SHIFT;
414 break;
415 }
416
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393 // Interrupt Acknowledge Register 0 |
394 case MISCREG_ICC_IAR0:
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418 case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
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395 case MISCREG_ICC_IAR0_EL1: { |
396 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 397 return readMiscReg(MISCREG_ICV_IAR0_EL1); 398 } 399 400 uint32_t int_id; 401 402 if (hppiCanPreempt()) { 403 int_id = getHPPIR0(); 404 405 // avoid activation for special interrupts 406 if (int_id < Gicv3::INTID_SECURE) { 407 activateIRQ(int_id, hppi.group); 408 } 409 } else { 410 int_id = Gicv3::INTID_SPURIOUS; 411 } 412 413 value = int_id; 414 break; 415 } 416
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417 // Virtual Interrupt Acknowledge Register 0 |
418 case MISCREG_ICV_IAR0_EL1: { 419 int lr_idx = getHPPVILR(); 420 uint32_t int_id = Gicv3::INTID_SPURIOUS; 421 422 if (lr_idx >= 0) {
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445 RegVal lr =
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423 ICH_LR_EL2 ich_lr_el2 = |
424 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 425
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448 if (!(lr & ICH_LR_EL2_GROUP) && hppviCanPreempt(lr_idx)) {
449 int_id = value = bits(lr, 31, 0);
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426 if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 427 int_id = ich_lr_el2.vINTID; |
428 429 if (int_id < Gicv3::INTID_SECURE ||
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452 int_id > Gicv3::INTID_SPURIOUS) {
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430 int_id > Gicv3::INTID_SPURIOUS) { |
431 virtualActivateIRQ(lr_idx); 432 } else { 433 // Bogus... Pseudocode says: 434 // - Move from pending to invalid... 435 // - Return de bogus id...
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458 lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
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436 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; |
437 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
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460 lr);
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438 ich_lr_el2); |
439 } 440 } 441 } 442 443 value = int_id; 444 virtualUpdate(); 445 break; 446 } 447
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448 // Interrupt Acknowledge Register 1 |
449 case MISCREG_ICC_IAR1:
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471 case MISCREG_ICC_IAR1_EL1: { // Interrupt Acknowledge Register 1
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450 case MISCREG_ICC_IAR1_EL1: { |
451 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 452 return readMiscReg(MISCREG_ICV_IAR1_EL1); 453 } 454 455 uint32_t int_id; 456 457 if (hppiCanPreempt()) { 458 int_id = getHPPIR1(); 459 460 // avoid activation for special interrupts 461 if (int_id < Gicv3::INTID_SECURE) { 462 activateIRQ(int_id, hppi.group); 463 }
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485
486 // LPIs are not activated and when acked their pending
487 // bit is cleared
488 if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID)
489 {
490 redistributor->setClrLPI(int_id, false);
491 }
492
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464 } else { 465 int_id = Gicv3::INTID_SPURIOUS; 466 } 467 468 value = int_id; 469 break; 470 } 471
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472 // Virtual Interrupt Acknowledge Register 1 |
473 case MISCREG_ICV_IAR1_EL1: { 474 int lr_idx = getHPPVILR(); 475 uint32_t int_id = Gicv3::INTID_SPURIOUS; 476 477 if (lr_idx >= 0) {
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506 RegVal lr =
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478 ICH_LR_EL2 ich_lr_el2 = |
479 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 480
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509 if (lr & ICH_LR_EL2_GROUP && hppviCanPreempt(lr_idx)) {
510 int_id = value = bits(lr, 31, 0);
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481 if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 482 int_id = ich_lr_el2.vINTID; |
483 484 if (int_id < Gicv3::INTID_SECURE ||
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513 int_id > Gicv3::INTID_SPURIOUS) {
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485 int_id > Gicv3::INTID_SPURIOUS) { |
486 virtualActivateIRQ(lr_idx); 487 } else { 488 // Bogus... Pseudocode says: 489 // - Move from pending to invalid... 490 // - Return de bogus id...
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519 lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
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491 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; |
492 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
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521 lr);
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493 ich_lr_el2); |
494 } 495 } 496 } 497 498 value = int_id; 499 virtualUpdate(); 500 break; 501 } 502
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503 // System Register Enable Register EL1 |
504 case MISCREG_ICC_SRE:
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532 case MISCREG_ICC_SRE_EL1: { // System Register Enable Register
533 bool dfb;
534 bool dib;
535
536 if (haveEL(EL3) && !distributor->DS) {
537 // DIB is RO alias of ICC_SRE_EL3.DIB
538 // DFB is RO alias of ICC_SRE_EL3.DFB
539 RegVal icc_sre_el3 =
540 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
541 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
542 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
543 } else if (haveEL(EL3) && distributor->DS) {
544 // DIB is RW alias of ICC_SRE_EL3.DIB
545 // DFB is RW alias of ICC_SRE_EL3.DFB
546 RegVal icc_sre_el3 =
547 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
548 dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
549 dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
550 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
551 // DIB is RO alias of ICC_SRE_EL2.DIB
552 // DFB is RO alias of ICC_SRE_EL2.DFB
553 RegVal icc_sre_el2 =
554 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL2);
555 dfb = icc_sre_el2 & ICC_SRE_EL2_DFB;
556 dib = icc_sre_el2 & ICC_SRE_EL2_DIB;
557 } else {
558 dfb = value & ICC_SRE_EL1_DFB;
559 dib = value & ICC_SRE_EL1_DIB;
560 }
561
562 value = ICC_SRE_EL1_SRE;
563
564 if (dfb) {
565 value |= ICC_SRE_EL1_DFB;
566 }
567
568 if (dib) {
569 value |= ICC_SRE_EL1_DIB;
570 }
571
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505 case MISCREG_ICC_SRE_EL1: { 506 /* 507 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 508 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 509 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 510 */ 511 ICC_SRE_EL1 icc_sre_el1 = 0; 512 icc_sre_el1.SRE = 1; 513 icc_sre_el1.DIB = 1; 514 icc_sre_el1.DFB = 1; 515 value = icc_sre_el1; |
516 break; 517 } 518
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519 // System Register Enable Register EL2 |
520 case MISCREG_ICC_HSRE:
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576 case MISCREG_ICC_SRE_EL2: // System Register Enable Register
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521 case MISCREG_ICC_SRE_EL2: { |
522 /* 523 * Enable [3] == 1
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579 * (Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL2,
580 * RAO/WI)
|
524 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) |
525 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 526 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 527 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 528 */
|
585 value = ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_DIB | ICC_SRE_EL2_DFB |
586 ICC_SRE_EL2_SRE;
|
529 ICC_SRE_EL2 icc_sre_el2 = 0; 530 icc_sre_el2.SRE = 1; 531 icc_sre_el2.DIB = 1; 532 icc_sre_el2.DFB = 1; 533 icc_sre_el2.Enable = 1; 534 value = icc_sre_el2; |
535 break;
|
536 } |
537
|
538 // System Register Enable Register EL3 |
539 case MISCREG_ICC_MSRE:
|
590 case MISCREG_ICC_SRE_EL3: // System Register Enable Register
|
540 case MISCREG_ICC_SRE_EL3: { |
541 /* 542 * Enable [3] == 1
|
593 * (Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL3,
594 * RAO/WI)
|
543 * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 544 * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 545 * RAO/WI) |
546 * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 547 * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 548 * SRE [0] == 1 (Only system register interface supported, RAO/WI) 549 */
|
599 value = ICC_SRE_EL3_ENABLE | ICC_SRE_EL3_DIB | ICC_SRE_EL3_DFB |
600 ICC_SRE_EL3_SRE;
|
550 ICC_SRE_EL3 icc_sre_el3 = 0; 551 icc_sre_el3.SRE = 1; 552 icc_sre_el3.DIB = 1; 553 icc_sre_el3.DFB = 1; 554 icc_sre_el3.Enable = 1; 555 value = icc_sre_el3; |
556 break;
|
557 } |
558
|
559 // Control Register |
560 case MISCREG_ICC_CTLR:
|
604 case MISCREG_ICC_CTLR_EL1: { // Control Register
605 if ((currEL() == EL1) && !inSecureState() &&
606 (hcr_imo || hcr_fmo)) {
|
561 case MISCREG_ICC_CTLR_EL1: { 562 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { |
563 return readMiscReg(MISCREG_ICV_CTLR_EL1); 564 } 565
|
610 // Add value for RO bits
|
566 // Enforce value for RO bits 567 // ExtRange [19], INTIDs in the range 1024..8191 not supported 568 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 569 // A3V [15], supports non-zero values of the Aff3 field in SGI 570 // generation System registers 571 // SEIS [14], does not support generation of SEIs (deprecated) |
572 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 573 // PRIbits [10:8], number of priority bits implemented, minus one
|
613 value |= ICC_CTLR_EL1_RSS | ICC_CTLR_EL1_A3V |
614 (1 << 11) | ((PRIORITY_BITS - 1) << 8);
|
574 ICC_CTLR_EL1 icc_ctlr_el1 = value; 575 icc_ctlr_el1.ExtRange = 0; 576 icc_ctlr_el1.RSS = 1; 577 icc_ctlr_el1.A3V = 1; 578 icc_ctlr_el1.SEIS = 0; 579 icc_ctlr_el1.IDbits = 1; 580 icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 581 value = icc_ctlr_el1; |
582 break; 583 } 584
|
585 // Virtual Control Register |
586 case MISCREG_ICV_CTLR_EL1: {
|
619 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
620 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
621 RegVal ich_vmcr_el2 =
622 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
623
624 if (ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
625 value |= ICC_CTLR_EL1_EOIMODE;
626 }
627
628 if (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
629 value |= ICC_CTLR_EL1_CBPR;
630 }
631
|
587 ICV_CTLR_EL1 icv_ctlr_el1 = value; 588 icv_ctlr_el1.RSS = 0; 589 icv_ctlr_el1.A3V = 1; 590 icv_ctlr_el1.SEIS = 0; 591 icv_ctlr_el1.IDbits = 1; 592 icv_ctlr_el1.PRIbits = 7; 593 value = icv_ctlr_el1; |
594 break; 595 } 596
|
597 // Control Register |
598 case MISCREG_ICC_MCTLR: 599 case MISCREG_ICC_CTLR_EL3: {
|
637 // Add value for RO bits
638 // RSS [18]
639 // A3V [15]
|
600 // Enforce value for RO bits 601 // ExtRange [19], INTIDs in the range 1024..8191 not supported 602 // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 603 // nDS [17], supports disabling of security 604 // A3V [15], supports non-zero values of the Aff3 field in SGI 605 // generation System registers 606 // SEIS [14], does not support generation of SEIs (deprecated) |
607 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 608 // PRIbits [10:8], number of priority bits implemented, minus one
|
642 value |= ICC_CTLR_EL3_RSS | ICC_CTLR_EL3_A3V | (0 << 11) |
643 ((PRIORITY_BITS - 1) << 8);
644 // Aliased bits...
645 RegVal icc_ctlr_el1_ns =
646 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
647 RegVal icc_ctlr_el1_s =
648 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
649
650 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_EOIMODE) {
651 value |= ICC_CTLR_EL3_EOIMODE_EL1NS;
652 }
653
654 if (icc_ctlr_el1_ns & ICC_CTLR_EL1_CBPR) {
655 value |= ICC_CTLR_EL3_CBPR_EL1NS;
656 }
657
658 if (icc_ctlr_el1_s & ICC_CTLR_EL1_EOIMODE) {
659 value |= ICC_CTLR_EL3_EOIMODE_EL1S;
660 }
661
662 if (icc_ctlr_el1_s & ICC_CTLR_EL1_CBPR) {
663 value |= ICC_CTLR_EL3_CBPR_EL1S;
664 }
665
|
609 ICC_CTLR_EL3 icc_ctlr_el3 = value; 610 icc_ctlr_el3.ExtRange = 0; 611 icc_ctlr_el3.RSS = 1; 612 icc_ctlr_el3.nDS = 0; 613 icc_ctlr_el3.A3V = 1; 614 icc_ctlr_el3.SEIS = 0; 615 icc_ctlr_el3.IDbits = 0; 616 icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 617 value = icc_ctlr_el3; |
618 break; 619 } 620
|
621 // Hyp Control Register |
622 case MISCREG_ICH_HCR: 623 case MISCREG_ICH_HCR_EL2: 624 break; 625
|
626 // Hyp Active Priorities Group 0 Registers |
627 case MISCREG_ICH_AP0R0: 628 case MISCREG_ICH_AP0R0_EL2: 629 break; 630
|
631 // Hyp Active Priorities Group 1 Registers |
632 case MISCREG_ICH_AP1R0: 633 case MISCREG_ICH_AP1R0_EL2: 634 break; 635
|
636 // Maintenance Interrupt State Register |
637 case MISCREG_ICH_MISR:
|
682 case MISCREG_ICH_MISR_EL2: {
683 value = 0;
684 // Scan list registers and fill in the U, NP and EOI bits
685 eoiMaintenanceInterruptStatus((uint32_t *) &value);
686 RegVal ich_hcr_el2 =
687 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
688 RegVal ich_vmcr_el2 =
689 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
|
638 case MISCREG_ICH_MISR_EL2: 639 value = maintenanceInterruptStatus(); 640 break; |
641
|
691 if (ich_hcr_el2 &
692 (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
693 value |= ICH_MISR_EL2_LRENP;
694 }
|
642 // VGIC Type Register 643 case MISCREG_ICH_VTR: 644 case MISCREG_ICH_VTR_EL2: { 645 ICH_VTR_EL2 ich_vtr_el2 = value; |
646
|
696 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
697 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
698 value |= ICH_MISR_EL2_VGRP0E;
699 }
|
647 ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 648 ich_vtr_el2.A3V = 1; 649 ich_vtr_el2.IDbits = 1; 650 ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 651 ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; |
652
|
701 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
702 !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
703 value |= ICH_MISR_EL2_VGRP0D;
704 }
705
706 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
707 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
708 value |= ICH_MISR_EL2_VGRP1E;
709 }
710
711 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
712 !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
713 value |= ICH_MISR_EL2_VGRP1D;
714 }
715
716 break;
|
653 value = ich_vtr_el2; 654 break; |
655 } 656
|
719 case MISCREG_ICH_VTR:
720 case MISCREG_ICH_VTR_EL2:
721 /*
722 * PRIbits [31:29]
723 * PREbits [28:26]
724 * IDbits [25:23]
725 * SEIS [22] == 0 (SEI Support)
726 * A3V [21] == 1
727 * (Non-zero values supported for Affinity 3 in SGI genearion)
728 * nV4 [20] == 0
729 * (Support for direct injection of virtual interrupts)
730 * TDS [19] == 0 (Implementation supports ICH_HCR_EL2.TDIR)
731 * ListRegs [4:0]
732 */
733 value = (16 - 1) << 0 |
734 (5 - 1) << 26 |
735 (5 - 1) << 29;
736 value =
737 ((VIRTUAL_NUM_LIST_REGS - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) |
738 // ICH_VTR_EL2_TDS |
739 // ICH_VTR_EL2_NV4 |
740 ICH_VTR_EL2_A3V |
741 (1 << ICH_VTR_EL2_IDBITS_SHIFT) |
742 ((VIRTUAL_PREEMPTION_BITS - 1) << ICH_VTR_EL2_PREBITS_SHIFT) |
743 ((VIRTUAL_PRIORITY_BITS - 1) << ICH_VTR_EL2_PRIBITS_SHIFT);
744 break;
745
|
657 // End of Interrupt Status Register |
658 case MISCREG_ICH_EISR: 659 case MISCREG_ICH_EISR_EL2:
|
748 value = eoiMaintenanceInterruptStatus(nullptr);
|
660 value = eoiMaintenanceInterruptStatus(); |
661 break; 662
|
663 // Empty List Register Status Register |
664 case MISCREG_ICH_ELRSR: 665 case MISCREG_ICH_ELRSR_EL2: 666 value = 0; 667 668 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
|
756 RegVal lr =
|
669 ICH_LR_EL2 ich_lr_el2 = |
670 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 671
|
759 if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
760 ((lr & ICH_LR_EL2_HW) != 0 ||
761 (lr & ICH_LR_EL2_EOI) == 0)) {
|
672 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 673 (ich_lr_el2.HW || !ich_lr_el2.EOI)) { |
674 value |= (1 << lr_idx); 675 } 676 } 677 678 break; 679
|
680 // List Registers |
681 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 682 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 683 value = value >> 32; 684 break; 685
|
686 // List Registers |
687 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 688 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 689 value = value & 0xffffffff; 690 break; 691
|
692 // List Registers |
693 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 694 break; 695
|
696 // Virtual Machine Control Register |
697 case MISCREG_ICH_VMCR: 698 case MISCREG_ICH_VMCR_EL2: 699 break; 700 701 default:
|
786 panic("Gicv3CPUInterface::readMiscReg(): "
787 "unknown register %d (%s)",
788 misc_reg, miscRegName[misc_reg]);
|
702 panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 703 misc_reg, miscRegName[misc_reg]); |
704 } 705
|
791 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): "
792 "register %s value %#x\n", miscRegName[misc_reg], value);
|
706 DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 707 miscRegName[misc_reg], value); |
708 return value; 709} 710 711void 712Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 713{ 714 bool do_virtual_update = false;
|
800 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): "
801 "register %s value %#x\n", miscRegName[misc_reg], val);
|
715 DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 716 miscRegName[misc_reg], val); |
717 bool hcr_fmo = getHCREL2FMO(); 718 bool hcr_imo = getHCREL2IMO(); 719 720 switch (misc_reg) {
|
721 // Active Priorities Group 1 Registers |
722 case MISCREG_ICC_AP1R0: 723 case MISCREG_ICC_AP1R0_EL1: 724 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 725 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 726 } 727 728 break; 729 730 case MISCREG_ICC_AP1R1: 731 case MISCREG_ICC_AP1R1_EL1: 732 733 // only implemented if supporting 6 or more bits of priority 734 case MISCREG_ICC_AP1R2: 735 case MISCREG_ICC_AP1R2_EL1: 736 737 // only implemented if supporting 7 or more bits of priority 738 case MISCREG_ICC_AP1R3: 739 case MISCREG_ICC_AP1R3_EL1: 740 // only implemented if supporting 7 or more bits of priority 741 break; 742
|
743 // Active Priorities Group 0 Registers |
744 case MISCREG_ICC_AP0R0: 745 case MISCREG_ICC_AP0R0_EL1: 746 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 747 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 748 } 749 750 break; 751 752 case MISCREG_ICC_AP0R1: 753 case MISCREG_ICC_AP0R1_EL1: 754 755 // only implemented if supporting 6 or more bits of priority 756 case MISCREG_ICC_AP0R2: 757 case MISCREG_ICC_AP0R2_EL1: 758 759 // only implemented if supporting 7 or more bits of priority 760 case MISCREG_ICC_AP0R3: 761 case MISCREG_ICC_AP0R3_EL1: 762 // only implemented if supporting 7 or more bits of priority 763 break; 764
|
765 // End Of Interrupt Register 0 |
766 case MISCREG_ICC_EOIR0: 767 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 768 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 769 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 770 } 771 772 int int_id = val & 0xffffff; 773 774 // avoid activation for special interrupts 775 if (int_id >= Gicv3::INTID_SECURE) { 776 return; 777 } 778 779 Gicv3::GroupId group = Gicv3::G0S; 780 781 if (highestActiveGroup() != group) { 782 return; 783 } 784 785 dropPriority(group); 786 787 if (!isEOISplitMode()) { 788 deactivateIRQ(int_id, group); 789 } 790 791 break; 792 } 793
|
794 // Virtual End Of Interrupt Register 0 |
795 case MISCREG_ICV_EOIR0_EL1: { 796 int int_id = val & 0xffffff; 797 798 // avoid deactivation for special interrupts 799 if (int_id >= Gicv3::INTID_SECURE && 800 int_id <= Gicv3::INTID_SPURIOUS) { 801 return; 802 } 803 804 uint8_t drop_prio = virtualDropPriority(); 805 806 if (drop_prio == 0xff) { 807 return; 808 } 809 810 int lr_idx = virtualFindActive(int_id); 811 812 if (lr_idx < 0) { 813 // No LR found matching 814 virtualIncrementEOICount(); 815 } else {
|
897 RegVal lr =
|
816 ICH_LR_EL2 ich_lr_el2 = |
817 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 818 Gicv3::GroupId lr_group =
|
900 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
901 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
|
819 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 820 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; |
821 822 if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
|
904 //JAIRO if (!virtualIsEOISplitMode())
|
823 //if (!virtualIsEOISplitMode()) |
824 { 825 virtualDeactivateIRQ(lr_idx); 826 } 827 } 828 } 829 830 virtualUpdate(); 831 break; 832 } 833
|
834 // End Of Interrupt Register 1 |
835 case MISCREG_ICC_EOIR1:
|
916 case MISCREG_ICC_EOIR1_EL1: { // End Of Interrupt Register 1
|
836 case MISCREG_ICC_EOIR1_EL1: { |
837 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 838 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 839 } 840 841 int int_id = val & 0xffffff; 842 843 // avoid deactivation for special interrupts 844 if (int_id >= Gicv3::INTID_SECURE) { 845 return; 846 } 847
|
928 Gicv3::GroupId group =
929 inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
|
848 Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; |
849 850 if (highestActiveGroup() == Gicv3::G0S) { 851 return; 852 } 853 854 if (distributor->DS == 0) { 855 if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 856 return; 857 } else if (highestActiveGroup() == Gicv3::G1NS &&
|
939 !(!inSecureState() or (currEL() == EL3))) {
|
858 !(!inSecureState() or (currEL() == EL3))) { |
859 return; 860 } 861 } 862 863 dropPriority(group); 864 865 if (!isEOISplitMode()) { 866 deactivateIRQ(int_id, group); 867 } 868 869 break; 870 } 871
|
872 // Virtual End Of Interrupt Register 1 |
873 case MISCREG_ICV_EOIR1_EL1: { 874 int int_id = val & 0xffffff; 875 876 // avoid deactivation for special interrupts 877 if (int_id >= Gicv3::INTID_SECURE &&
|
958 int_id <= Gicv3::INTID_SPURIOUS) {
|
878 int_id <= Gicv3::INTID_SPURIOUS) { |
879 return; 880 } 881 882 uint8_t drop_prio = virtualDropPriority(); 883 884 if (drop_prio == 0xff) { 885 return; 886 } 887 888 int lr_idx = virtualFindActive(int_id); 889 890 if (lr_idx < 0) {
|
971 // No LR found matching
|
891 // No matching LR found |
892 virtualIncrementEOICount(); 893 } else {
|
974 RegVal lr =
|
894 ICH_LR_EL2 ich_lr_el2 = |
895 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 896 Gicv3::GroupId lr_group =
|
977 lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
978 uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
|
897 ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 898 uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; |
899 900 if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 901 if (!virtualIsEOISplitMode()) { 902 virtualDeactivateIRQ(lr_idx); 903 } 904 } 905 } 906 907 virtualUpdate(); 908 break; 909 } 910
|
911 // Deactivate Interrupt Register |
912 case MISCREG_ICC_DIR:
|
992 case MISCREG_ICC_DIR_EL1: { // Deactivate Interrupt Register
|
913 case MISCREG_ICC_DIR_EL1: { |
914 if ((currEL() == EL1) && !inSecureState() &&
|
994 (hcr_imo || hcr_fmo)) {
|
915 (hcr_imo || hcr_fmo)) { |
916 return setMiscReg(MISCREG_ICV_DIR_EL1, val); 917 } 918 919 int int_id = val & 0xffffff; 920
|
1000 // avoid deactivation for special interrupts
|
921 // The following checks are as per spec pseudocode 922 // aarch64/support/ICC_DIR_EL1 923 924 // Check for spurious ID |
925 if (int_id >= Gicv3::INTID_SECURE) { 926 return; 927 } 928
|
929 // EOI mode is not set, so don't deactivate |
930 if (!isEOISplitMode()) { 931 return; 932 } 933
|
1009 /*
1010 * Check whether we're allowed to deactivate.
1011 * These checks are correspond to the spec's pseudocode.
1012 */
|
934 Gicv3::GroupId group = 935 int_id >= 32 ? distributor->getIntGroup(int_id) : 936 redistributor->getIntGroup(int_id); 937 bool irq_is_grp0 = group == Gicv3::G0S; 938 bool single_sec_state = distributor->DS; 939 bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 940 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 941 bool route_fiq_to_el3 = scr_el3.fiq; 942 bool route_irq_to_el3 = scr_el3.irq; 943 bool route_fiq_to_el2 = hcr_fmo; 944 bool route_irq_to_el2 = hcr_imo; 945 946 switch (currEL()) { 947 case EL3: 948 break; 949 950 case EL2: 951 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 952 break; 953 } 954 955 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 956 break; 957 } 958 959 return; 960 961 case EL1: 962 if (!isSecureBelowEL3()) { 963 if (single_sec_state && irq_is_grp0 &&
|
1043 !route_fiq_to_el3 && !route_fiq_to_el2) {
|
964 !route_fiq_to_el3 && !route_fiq_to_el2) { |
965 break; 966 } 967 968 if (!irq_is_secure && !irq_is_grp0 &&
|
1048 !route_irq_to_el3 && !route_irq_to_el2) {
|
969 !route_irq_to_el3 && !route_irq_to_el2) { |
970 break; 971 } 972 } else { 973 if (irq_is_grp0 && !route_fiq_to_el3) { 974 break; 975 } 976 977 if (!irq_is_grp0 &&
|
1057 (!irq_is_secure || !single_sec_state) &&
1058 !route_irq_to_el3) {
|
978 (!irq_is_secure || !single_sec_state) && 979 !route_irq_to_el3) { |
980 break; 981 } 982 } 983 984 return; 985 986 default: 987 break; 988 } 989 990 deactivateIRQ(int_id, group); 991 break; 992 } 993
|
994 // Deactivate Virtual Interrupt Register |
995 case MISCREG_ICV_DIR_EL1: { 996 int int_id = val & 0xffffff; 997 998 // avoid deactivation for special interrupts 999 if (int_id >= Gicv3::INTID_SECURE &&
|
1078 int_id <= Gicv3::INTID_SPURIOUS) {
|
1000 int_id <= Gicv3::INTID_SPURIOUS) { |
1001 return; 1002 } 1003 1004 if (!virtualIsEOISplitMode()) { 1005 return; 1006 } 1007 1008 int lr_idx = virtualFindActive(int_id); 1009 1010 if (lr_idx < 0) {
|
1089 // No LR found matching
|
1011 // No matching LR found |
1012 virtualIncrementEOICount(); 1013 } else { 1014 virtualDeactivateIRQ(lr_idx); 1015 } 1016 1017 virtualUpdate(); 1018 break; 1019 } 1020
|
1021 // Binary Point Register 0 |
1022 case MISCREG_ICC_BPR0:
|
1100 case MISCREG_ICC_BPR0_EL1: // Binary Point Register 0
|
1023 case MISCREG_ICC_BPR0_EL1: 1024 // Binary Point Register 1 |
1025 case MISCREG_ICC_BPR1:
|
1102 case MISCREG_ICC_BPR1_EL1: { // Binary Point Register 1
|
1026 case MISCREG_ICC_BPR1_EL1: { |
1027 if ((currEL() == EL1) && !inSecureState()) { 1028 if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) { 1029 return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 1030 } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) { 1031 return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 1032 } 1033 } 1034 1035 Gicv3::GroupId group = 1036 misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 1037 1038 if (group == Gicv3::G1S && !inSecureState()) { 1039 group = Gicv3::G1NS; 1040 } 1041
|
1118 if ((group == Gicv3::G1S) &&
1119 !isEL3OrMon() &&
1120 (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S) &
1121 ICC_CTLR_EL1_CBPR)) {
|
1042 ICC_CTLR_EL1 icc_ctlr_el1_s = 1043 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1044 1045 if ((group == Gicv3::G1S) && !isEL3OrMon() && 1046 icc_ctlr_el1_s.CBPR) { |
1047 group = Gicv3::G0S; 1048 } 1049
|
1125 if ((group == Gicv3::G1NS) &&
1126 (currEL() < EL3) &&
1127 (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS) &
1128 ICC_CTLR_EL1_CBPR)) {
1129 // Reads return BPR0 + 1 saturated to 7, WI
|
1050 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1051 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 1052 1053 if ((group == Gicv3::G1NS) && (currEL() < EL3) && 1054 icc_ctlr_el1_ns.CBPR) { 1055 // BPR0 + 1 saturated to 7, WI |
1056 return; 1057 } 1058 1059 uint8_t min_val = (group == Gicv3::G1NS) ? 1060 GIC_MIN_BPR_NS : GIC_MIN_BPR; 1061 val &= 0x7; 1062 1063 if (val < min_val) { 1064 val = min_val; 1065 } 1066 1067 break; 1068 } 1069
|
1070 // Virtual Binary Point Register 0 |
1071 case MISCREG_ICV_BPR0_EL1:
|
1072 // Virtual Binary Point Register 1 |
1073 case MISCREG_ICV_BPR1_EL1: { 1074 Gicv3::GroupId group = 1075 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
|
1148 RegVal ich_vmcr_el2 =
|
1076 ICH_VMCR_EL2 ich_vmcr_el2 = |
1077 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1078
|
1151 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
1152 // reads return bpr0 + 1 saturated to 7, writes ignored
|
1079 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 1080 // BPR0 + 1 saturated to 7, WI |
1081 return; 1082 } 1083 1084 uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 1085 1086 if (group != Gicv3::G0S) { 1087 min_VPBR++; 1088 } 1089 1090 if (val < min_VPBR) { 1091 val = min_VPBR; 1092 } 1093 1094 if (group == Gicv3::G0S) {
|
1167 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1168 ICH_VMCR_EL2_VBPR0_SHIFT + 2, ICH_VMCR_EL2_VBPR0_SHIFT,
1169 val);
|
1095 ich_vmcr_el2.VBPR0 = val; |
1096 } else {
|
1171 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1172 ICH_VMCR_EL2_VBPR1_SHIFT + 2, ICH_VMCR_EL2_VBPR1_SHIFT,
1173 val);
|
1097 ich_vmcr_el2.VBPR1 = val; |
1098 } 1099 1100 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1101 do_virtual_update = true; 1102 break; 1103 } 1104
|
1105 // Control Register EL1 |
1106 case MISCREG_ICC_CTLR:
|
1182 case MISCREG_ICC_CTLR_EL1: { // Control Register
1183 if ((currEL() == EL1) && !inSecureState() &&
1184 (hcr_imo || hcr_fmo)) {
|
1107 case MISCREG_ICC_CTLR_EL1: { 1108 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { |
1109 return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 1110 } 1111 1112 /*
|
1113 * ExtRange is RO. |
1114 * RSS is RO. 1115 * A3V is RO. 1116 * SEIS is RO. 1117 * IDbits is RO. 1118 * PRIbits is RO.
|
1194 * If EL3 is implemented and GICD_CTLR.DS == 0, then PMHE is RO.
1195 * So, only CBPR[0] and EOIMODE[1] are RW.
1196 * If EL3 is implemented and GICD_CTLR.DS == 0, then CBPR is RO.
|
1119 */
|
1198 uint64_t mask;
|
1120 ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 1121 ICC_CTLR_EL1 icc_ctlr_el1 = 1122 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); |
1123
|
1200 if (haveEL(EL3) and distributor->DS == 0) {
1201 mask = ICC_CTLR_EL1_EOIMODE;
1202 } else if (haveEL(EL3) and distributor->DS == 1) {
1203 mask = ICC_CTLR_EL1_PMHE | ICC_CTLR_EL1_CBPR |
1204 ICC_CTLR_EL1_EOIMODE;
|
1124 ICC_CTLR_EL3 icc_ctlr_el3 = 1125 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1126 1127 // The following could be refactored but it is following 1128 // spec description section 9.2.6 point by point. 1129 1130 // PMHE 1131 if (haveEL(EL3)) { 1132 // PMHE is alias of ICC_CTLR_EL3.PMHE 1133 1134 if (distributor->DS == 0) { 1135 // PMHE is RO 1136 } else if (distributor->DS == 1) { 1137 // PMHE is RW 1138 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 1139 icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 1140 } |
1141 } else {
|
1206 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
|
1142 // PMHE is RW (by implementation choice) 1143 icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; |
1144 } 1145
|
1209 RegVal old_val =
1210 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
1211 old_val &= ~mask;
1212 val = old_val | (val & mask);
|
1146 // EOImode 1147 icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 1148 1149 if (inSecureState()) { 1150 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 1151 icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 1152 } else { 1153 // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 1154 icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 1155 } 1156 1157 // CBPR 1158 if (haveEL(EL3)) { 1159 // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 1160 1161 if (distributor->DS == 0) { 1162 // CBPR is RO 1163 } else { 1164 // CBPR is RW 1165 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 1166 1167 if (inSecureState()) { 1168 icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 1169 } else { 1170 icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 1171 } 1172 } 1173 } else { 1174 // CBPR is RW 1175 icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 1176 } 1177 1178 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 1179 1180 val = icc_ctlr_el1; |
1181 break; 1182 } 1183
|
1184 // Virtual Control Register |
1185 case MISCREG_ICV_CTLR_EL1: {
|
1217 RegVal ich_vmcr_el2 =
1218 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1219 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
1220 val & ICC_CTLR_EL1_CBPR ? 1 : 0);
1221 ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
1222 val & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
1223 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1224 do_virtual_update = true;
1225 break;
|
1186 ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 1187 ICV_CTLR_EL1 icv_ctlr_el1 = 1188 isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 1189 icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 1190 icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 1191 val = icv_ctlr_el1; 1192 1193 // Aliases 1194 // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 1195 // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 1196 ICH_VMCR_EL2 ich_vmcr_el2 = 1197 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1198 ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 1199 ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 1200 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1201 break; |
1202 } 1203
|
1204 // Control Register EL3 |
1205 case MISCREG_ICC_MCTLR: 1206 case MISCREG_ICC_CTLR_EL3: {
|
1230 RegVal icc_ctlr_el1_s =
1231 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
1232 RegVal icc_ctlr_el1_ns =
1233 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
|
1207 /* 1208 * ExtRange is RO. 1209 * RSS is RO. 1210 * nDS is RO. 1211 * A3V is RO. 1212 * SEIS is RO. 1213 * IDbits is RO. 1214 * PRIbits is RO. 1215 * PMHE is RAO/WI, priority-based routing is always used. 1216 */ 1217 ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; |
1218
|
1235 // ICC_CTLR_EL1(NS).EOImode is an alias of
1236 // ICC_CTLR_EL3.EOImode_EL1NS
1237 if (val & ICC_CTLR_EL3_EOIMODE_EL1NS) {
1238 icc_ctlr_el1_ns |= ICC_CTLR_EL1_EOIMODE;
1239 } else {
1240 icc_ctlr_el1_ns &= ~ICC_CTLR_EL1_EOIMODE;
1241 }
|
1219 // Aliases 1220 if (haveEL(EL3)) 1221 { 1222 ICC_CTLR_EL1 icc_ctlr_el1_s = 1223 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1224 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1225 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); |
1226
|
1243 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS
1244 if (val & ICC_CTLR_EL3_CBPR_EL1NS) {
1245 icc_ctlr_el1_ns |= ICC_CTLR_EL1_CBPR;
1246 } else {
1247 icc_ctlr_el1_ns &= ~ICC_CTLR_EL1_CBPR;
1248 }
|
1227 // ICC_CTLR_EL1(NS).EOImode is an alias of 1228 // ICC_CTLR_EL3.EOImode_EL1NS 1229 icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 1230 // ICC_CTLR_EL1(S).EOImode is an alias of 1231 // ICC_CTLR_EL3.EOImode_EL1S 1232 icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 1233 // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 1234 icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 1235 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 1236 icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; |
1237
|
1250 // ICC_CTLR_EL1(S).EOImode is an alias of ICC_CTLR_EL3.EOImode_EL1S
1251 if (val & ICC_CTLR_EL3_EOIMODE_EL1S) {
1252 icc_ctlr_el1_s |= ICC_CTLR_EL1_EOIMODE;
1253 } else {
1254 icc_ctlr_el1_s &= ~ICC_CTLR_EL1_EOIMODE;
|
1238 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 1239 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 1240 icc_ctlr_el1_ns); |
1241 } 1242
|
1257 // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S
1258 if (val & ICC_CTLR_EL3_CBPR_EL1S) {
1259 icc_ctlr_el1_s |= ICC_CTLR_EL1_CBPR;
1260 } else {
1261 icc_ctlr_el1_s &= ~ICC_CTLR_EL1_CBPR;
1262 }
1263
1264 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
1265 isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, icc_ctlr_el1_ns);
1266 // Only ICC_CTLR_EL3_EOIMODE_EL3 is writable
1267 RegVal old_icc_ctlr_el3 =
|
1243 ICC_CTLR_EL3 icc_ctlr_el3 = |
1244 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
|
1269 old_icc_ctlr_el3 &= ~(ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM);
1270 val = old_icc_ctlr_el3 |
1271 (val & (ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM));
|
1245 1246 icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 1247 icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 1248 icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 1249 icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 1250 icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 1251 icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 1252 1253 val = icc_ctlr_el3; |
1254 break; 1255 } 1256
|
1257 // Priority Mask Register |
1258 case MISCREG_ICC_PMR:
|
1276 case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
1277 if ((currEL() == EL1) && !inSecureState() &&
1278 (hcr_imo || hcr_fmo)) {
1279 return setMiscReg(MISCREG_ICV_PMR_EL1, val);
|
1259 case MISCREG_ICC_PMR_EL1: { 1260 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 1261 return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val); |
1262 } 1263 1264 val &= 0xff; 1265 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 1266 1267 if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
|
1286 /*
1287 * NS access and Group 0 is inaccessible to NS: return the
1288 * NS view of the current priority
1289 */
|
1268 // Spec section 4.8.1 1269 // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: |
1270 RegVal old_icc_pmr_el1 = 1271 isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 1272 1273 if (!(old_icc_pmr_el1 & 0x80)) {
|
1294 /* Current PMR in the secure range, don't allow NS to
1295 * change it */
|
1274 // If the current priority mask value is in the range of 1275 // 0x00-0x7F then WI |
1276 return; 1277 } 1278
|
1279 // If the current priority mask value is in the range of 1280 // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 1281 // based on the Non-secure read of the priority mask value 1282 // written to the register. 1283 |
1284 val = (val >> 1) | 0x80; 1285 } 1286 1287 val &= ~0U << (8 - PRIORITY_BITS); 1288 break; 1289 } 1290
|
1306 case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
1307 RegVal ich_vmcr_el2 =
1308 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1309 ich_vmcr_el2 = insertBits(
1310 ich_vmcr_el2,
1311 ICH_VMCR_EL2_VPMR_SHIFT + ICH_VMCR_EL2_VPMR_LENGTH - 1,
1312 ICH_VMCR_EL2_VPMR_SHIFT, val);
1313
1314 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
1315 virtualUpdate();
1316 return;
1317 }
1318
|
1291 // Interrupt Group 0 Enable Register EL1 |
1292 case MISCREG_ICC_IGRPEN0:
|
1320 case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
|
1293 case MISCREG_ICC_IGRPEN0_EL1: { |
1294 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 1295 return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 1296 } 1297 1298 break; 1299 } 1300
|
1301 // Virtual Interrupt Group 0 Enable register |
1302 case MISCREG_ICV_IGRPEN0_EL1: { 1303 bool enable = val & 0x1;
|
1330 RegVal ich_vmcr_el2 =
|
1304 ICH_VMCR_EL2 ich_vmcr_el2 = |
1305 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
|
1332 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1333 ICH_VMCR_EL2_VENG0_SHIFT, enable);
|
1306 ich_vmcr_el2.VENG0 = enable; |
1307 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1308 virtualUpdate(); 1309 return; 1310 } 1311
|
1312 // Interrupt Group 1 Enable register EL1 |
1313 case MISCREG_ICC_IGRPEN1:
|
1340 case MISCREG_ICC_IGRPEN1_EL1: { // Interrupt Group 1 Enable Register
|
1314 case MISCREG_ICC_IGRPEN1_EL1: { |
1315 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 1316 return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 1317 } 1318
|
1319 if (haveEL(EL3)) { 1320 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 1321 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 1322 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 1323 1324 if (inSecureState()) { 1325 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 1326 icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 1327 } else { 1328 // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 1329 icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 1330 } 1331 1332 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 1333 icc_igrpen1_el3); 1334 } 1335 |
1336 break; 1337 } 1338
|
1339 // Virtual Interrupt Group 1 Enable register |
1340 case MISCREG_ICV_IGRPEN1_EL1: { 1341 bool enable = val & 0x1;
|
1350 RegVal ich_vmcr_el2 =
|
1342 ICH_VMCR_EL2 ich_vmcr_el2 = |
1343 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
|
1352 ich_vmcr_el2 = insertBits(ich_vmcr_el2,
1353 ICH_VMCR_EL2_VENG1_SHIFT, enable);
|
1344 ich_vmcr_el2.VENG1 = enable; |
1345 isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 1346 virtualUpdate(); 1347 return; 1348 } 1349
|
1350 // Interrupt Group 1 Enable register |
1351 case MISCREG_ICC_MGRPEN1: 1352 case MISCREG_ICC_IGRPEN1_EL3: {
|
1361 // EnableGrp1S and EnableGrp1NS are aliased with
1362 // ICC_IGRPEN1_EL1_S.Enable and ICC_IGRPEN1_EL1_NS.Enable
1363 bool enable_grp_1s = val & ICC_IGRPEN1_EL3_ENABLEGRP1S;
1364 bool enable_grp_1ns = val & ICC_IGRPEN1_EL3_ENABLEGRP1NS;
1365 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S, enable_grp_1s);
1366 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS, enable_grp_1ns);
1367 return;
|
1353 ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 1354 ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 1355 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 1356 1357 if (inSecureState()) { 1358 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 1359 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 1360 } else { 1361 // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 1362 icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 1363 } 1364 1365 isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 1366 break; |
1367 } 1368
|
1370 // Software Generated Interrupt Group 0 Register
|
1369 // Software Generated Interrupt Group 0 Register |
1370 case MISCREG_ICC_SGI0R: 1371 case MISCREG_ICC_SGI0R_EL1: 1372
|
1374 // Software Generated Interrupt Group 1 Register
|
1373 // Software Generated Interrupt Group 1 Register |
1374 case MISCREG_ICC_SGI1R: 1375 case MISCREG_ICC_SGI1R_EL1: 1376
|
1378 // Alias Software Generated Interrupt Group 1 Register
|
1377 // Alias Software Generated Interrupt Group 1 Register |
1378 case MISCREG_ICC_ASGI1R: 1379 case MISCREG_ICC_ASGI1R_EL1: { 1380 bool ns = !inSecureState(); 1381 Gicv3::GroupId group; 1382 1383 if (misc_reg == MISCREG_ICC_SGI1R_EL1) { 1384 group = ns ? Gicv3::G1NS : Gicv3::G1S; 1385 } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) { 1386 group = ns ? Gicv3::G1S : Gicv3::G1NS; 1387 } else { 1388 group = Gicv3::G0S; 1389 } 1390 1391 if (distributor->DS && group == Gicv3::G1S) { 1392 group = Gicv3::G0S; 1393 } 1394 1395 uint8_t aff3 = bits(val, 55, 48); 1396 uint8_t aff2 = bits(val, 39, 32); 1397 uint8_t aff1 = bits(val, 23, 16);; 1398 uint16_t target_list = bits(val, 15, 0); 1399 uint32_t int_id = bits(val, 27, 24); 1400 bool irm = bits(val, 40, 40); 1401 uint8_t rs = bits(val, 47, 44); 1402 1403 for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 1404 Gicv3Redistributor * redistributor_i = 1405 gic->getRedistributor(i); 1406 uint32_t affinity_i = redistributor_i->getAffinity(); 1407 1408 if (irm) { 1409 // Interrupts routed to all PEs in the system, 1410 // excluding "self" 1411 if (affinity_i == redistributor->getAffinity()) { 1412 continue; 1413 } 1414 } else { 1415 // Interrupts routed to the PEs specified by 1416 // Aff3.Aff2.Aff1.<target list> 1417 if ((affinity_i >> 8) !=
|
1419 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
|
1418 ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { |
1419 continue; 1420 } 1421 1422 uint8_t aff0_i = bits(affinity_i, 7, 0); 1423 1424 if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
|
1426 ((0x1 << (aff0_i - rs * 16)) & target_list))) {
|
1425 ((0x1 << (aff0_i - rs * 16)) & target_list))) { |
1426 continue; 1427 } 1428 } 1429 1430 redistributor_i->sendSGI(int_id, group, ns); 1431 } 1432 1433 break; 1434 } 1435
|
1436 // System Register Enable Register EL1 |
1437 case MISCREG_ICC_SRE:
|
1438 case MISCREG_ICC_SRE_EL1: { // System Register Enable Register EL1
1439 if (!(val & ICC_SRE_EL1_SRE)) {
1440 warn("Gicv3CPUInterface::setMiscReg(): "
1441 "ICC_SRE_EL*.SRE is RAO/WI, legacy not supported!\n");
1442 }
1443
1444 bool dfb = val & ICC_SRE_EL1_DFB;
1445 bool dib = val & ICC_SRE_EL1_DIB;
1446
1447 if (haveEL(EL3) && !distributor->DS) {
1448 // DIB is RO alias of ICC_SRE_EL3.DIB
1449 // DFB is RO alias of ICC_SRE_EL3.DFB
1450 } else if (haveEL(EL3) && distributor->DS) {
1451 // DIB is RW alias of ICC_SRE_EL3.DIB
1452 // DFB is RW alias of ICC_SRE_EL3.DFB
1453 RegVal icc_sre_el3 =
1454 isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
1455 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DFB, dfb);
1456 icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DIB, dib);
1457 isa->setMiscRegNoEffect(MISCREG_ICC_SRE_EL3, icc_sre_el3);
1458 } else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
1459 // DIB is RO alias of ICC_SRE_EL2.DIB
1460 // DFB is RO alias of ICC_SRE_EL2.DFB
1461 } else {
1462 isa->setMiscRegNoEffect(misc_reg, val);
1463 }
1464
1465 return;
1466 }
1467
|
1438 case MISCREG_ICC_SRE_EL1: 1439 // System Register Enable Register EL2 |
1440 case MISCREG_ICC_HSRE:
|
1469 case MISCREG_ICC_SRE_EL2: // System Register Enable Register EL2
|
1441 case MISCREG_ICC_SRE_EL2: 1442 // System Register Enable Register EL3 |
1443 case MISCREG_ICC_MSRE:
|
1471 case MISCREG_ICC_SRE_EL3: // System Register Enable Register EL3
1472 if (!(val & (1 << 0))) {
1473 warn("Gicv3CPUInterface::setMiscReg(): "
1474 "ICC_SRE_EL*.SRE is RAO/WI, legacy not supported!\n");
1475 }
1476
|
1444 case MISCREG_ICC_SRE_EL3: |
1445 // All bits are RAO/WI
|
1478 break;
|
1446 return; |
1447
|
1448 // Hyp Control Register |
1449 case MISCREG_ICH_HCR:
|
1481 case MISCREG_ICH_HCR_EL2:
1482 val &= ICH_HCR_EL2_EN | ICH_HCR_EL2_UIE | ICH_HCR_EL2_LRENPIE |
1483 ICH_HCR_EL2_NPIE | ICH_HCR_EL2_VGRP0EIE |
1484 ICH_HCR_EL2_VGRP0DIE | ICH_HCR_EL2_VGRP1EIE |
1485 ICH_HCR_EL2_VGRP1DIE | ICH_HCR_EL2_TC | ICH_HCR_EL2_TALL0 |
1486 ICH_HCR_EL2_TALL1 | ICH_HCR_EL2_TDIR |
1487 ICH_HCR_EL2_EOICOUNT_MASK;
|
1450 case MISCREG_ICH_HCR_EL2: { 1451 ICH_HCR_EL2 requested_ich_hcr_el2 = val; 1452 ICH_HCR_EL2 ich_hcr_el2 = 1453 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 1454 1455 if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 1456 { 1457 // EOIcount - Permitted behaviors are: 1458 // - Increment EOIcount. 1459 // - Leave EOIcount unchanged. 1460 ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 1461 } 1462 1463 ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 1464 ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 1465 ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 1466 ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 1467 ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 1468 ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 1469 ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 1470 ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 1471 ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 1472 ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 1473 ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 1474 ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 1475 ich_hcr_el2.En = requested_ich_hcr_el2.En; 1476 val = ich_hcr_el2; |
1477 do_virtual_update = true; 1478 break;
|
1479 } |
1480
|
1491 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
|
1481 // List Registers 1482 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { |
1483 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
|
1493 {
1494 // Enforce RES0 bits in priority field, 5 of 8 bits used
1495 val = insertBits(val, ICH_LRC_PRIORITY_SHIFT + 2,
1496 ICH_LRC_PRIORITY_SHIFT, 0);
1497 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1498 val = (old_val & 0xffffffff) | (val << 32);
1499 do_virtual_update = true;
1500 break;
|
1484 ICH_LRC requested_ich_lrc = val; 1485 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 1486 1487 ich_lrc.State = requested_ich_lrc.State; 1488 ich_lrc.HW = requested_ich_lrc.HW; 1489 ich_lrc.Group = requested_ich_lrc.Group; 1490 1491 // Priority, bits [23:16] 1492 // At least five bits must be implemented. 1493 // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 1494 // We implement 5 bits. 1495 ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 1496 (ich_lrc.Priority & 0x07); 1497 1498 // pINTID, bits [12:0] 1499 // When ICH_LR<n>.HW is 0 this field has the following meaning: 1500 // - Bits[12:10] : RES0. 1501 // - Bit[9] : EOI. 1502 // - Bits[8:0] : RES0. 1503 // When ICH_LR<n>.HW is 1: 1504 // - This field is only required to implement enough bits to hold a 1505 // valid value for the implemented INTID size. Any unused higher 1506 // order bits are RES0. 1507 if (requested_ich_lrc.HW == 0) { 1508 ich_lrc.EOI = requested_ich_lrc.EOI; 1509 } else { 1510 ich_lrc.pINTID = requested_ich_lrc.pINTID; |
1511 } 1512
|
1513 val = ich_lrc; 1514 do_virtual_update = true; 1515 break; 1516 } 1517 1518 // List Registers |
1519 case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 1520 // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 1521 RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 1522 val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 1523 do_virtual_update = true; 1524 break; 1525 } 1526
|
1527 // List Registers |
1528 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
|
1512 // Enforce RES0 bits in priority field, 5 of 8 bits used
1513 val = insertBits(val, ICH_LR_EL2_PRIORITY_SHIFT + 2,
1514 ICH_LR_EL2_PRIORITY_SHIFT, 0);
|
1529 ICH_LR_EL2 requested_ich_lr_el2 = val; 1530 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 1531 1532 ich_lr_el2.State = requested_ich_lr_el2.State; 1533 ich_lr_el2.HW = requested_ich_lr_el2.HW; 1534 ich_lr_el2.Group = requested_ich_lr_el2.Group; 1535 1536 // Priority, bits [55:48] 1537 // At least five bits must be implemented. 1538 // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 1539 // We implement 5 bits. 1540 ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 1541 (ich_lr_el2.Priority & 0x07); 1542 1543 // pINTID, bits [44:32] 1544 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 1545 // - Bits[44:42] : RES0. 1546 // - Bit[41] : EOI. 1547 // - Bits[40:32] : RES0. 1548 // When ICH_LR<n>_EL2.HW is 1: 1549 // - This field is only required to implement enough bits to hold a 1550 // valid value for the implemented INTID size. Any unused higher 1551 // order bits are RES0. 1552 if (requested_ich_lr_el2.HW == 0) { 1553 ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 1554 } else { 1555 ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 1556 } 1557 1558 // vINTID, bits [31:0] 1559 // It is IMPLEMENTATION DEFINED how many bits are implemented, 1560 // though at least 16 bits must be implemented. 1561 // Unimplemented bits are RES0. 1562 ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 1563 1564 val = ich_lr_el2; |
1565 do_virtual_update = true; 1566 break; 1567 } 1568
|
1569 // Virtual Machine Control Register |
1570 case MISCREG_ICH_VMCR: 1571 case MISCREG_ICH_VMCR_EL2: {
|
1521 val &= ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1 |
1522 ICH_VMCR_EL2_VCBPR | ICH_VMCR_EL2_VEOIM |
1523 ICH_VMCR_EL2_VBPR1_MASK | ICH_VMCR_EL2_VBPR0_MASK |
1524 ICH_VMCR_EL2_VPMR_MASK;
1525 val |= ICH_VMCR_EL2_VFIQEN; // RES1
1526 // Check VBPRs against minimun allowed value
1527 uint8_t vbpr0 = bits(val, 23, 21);
1528 uint8_t vbpr1 = bits(val, 20, 18);
|
1572 ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 1573 ICH_VMCR_EL2 ich_vmcr_el2 = 1574 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1575 ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; |
1576 uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS;
|
1577 1578 if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 1579 ich_vmcr_el2.VBPR0 = min_vpr0; 1580 } else { 1581 ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 1582 } 1583 |
1584 uint8_t min_vpr1 = min_vpr0 + 1;
|
1531 vbpr0 = vbpr0 < min_vpr0 ? min_vpr0 : vbpr0;
1532 vbpr1 = vbpr1 < min_vpr1 ? min_vpr1 : vbpr1;
1533 val = insertBits(val, ICH_VMCR_EL2_VBPR0_SHIFT + 2,
1534 ICH_VMCR_EL2_VBPR0_SHIFT, vbpr0);
1535 val = insertBits(val, ICH_VMCR_EL2_VBPR1_SHIFT + 2,
1536 ICH_VMCR_EL2_VBPR1_SHIFT, vbpr1);
|
1585 1586 if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 1587 ich_vmcr_el2.VBPR1 = min_vpr1; 1588 } else { 1589 ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 1590 } 1591 1592 ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 1593 ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 1594 ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 1595 ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 1596 val = ich_vmcr_el2; |
1597 break; 1598 } 1599
|
1600 // Hyp Active Priorities Group 0 Registers |
1601 case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3: 1602 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
|
1603 // Hyp Active Priorities Group 1 Registers |
1604 case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3: 1605 case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2: 1606 break; 1607 1608 default:
|
1547 panic("Gicv3CPUInterface::setMiscReg(): "
1548 "unknown register %d (%s)",
1549 misc_reg, miscRegName[misc_reg]);
|
1609 panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 1610 misc_reg, miscRegName[misc_reg]); |
1611 } 1612 1613 isa->setMiscRegNoEffect(misc_reg, val); 1614 1615 if (do_virtual_update) { 1616 virtualUpdate(); 1617 } 1618} 1619 1620int
|
1560Gicv3CPUInterface::virtualFindActive(uint32_t int_id)
|
1621Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const |
1622{ 1623 for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
|
1563 RegVal lr =
|
1624 ICH_LR_EL2 ich_lr_el2 = |
1625 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
|
1565 uint32_t lr_intid = bits(lr, 31, 0);
|
1626
|
1567 if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && lr_intid == int_id) {
|
1627 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 1628 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 1629 (ich_lr_el2.vINTID == int_id)) { |
1630 return lr_idx; 1631 } 1632 } 1633 1634 return -1; 1635} 1636 1637uint32_t
|
1576Gicv3CPUInterface::getHPPIR0()
|
1638Gicv3CPUInterface::getHPPIR0() const |
1639{ 1640 if (hppi.prio == 0xff) { 1641 return Gicv3::INTID_SPURIOUS; 1642 } 1643 1644 bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 1645 1646 if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
|
1585 /* Indicate to EL3 that there's a Group 1 interrupt for the
1586 * other state pending.
1587 */
|
1647 // interrupt for the other state pending |
1648 return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 1649 } 1650 1651 if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 1652 return Gicv3::INTID_SPURIOUS; 1653 } 1654 1655 if (irq_is_secure && !inSecureState()) { 1656 // Secure interrupts not visible in Non-secure 1657 return Gicv3::INTID_SPURIOUS; 1658 } 1659 1660 return hppi.intid; 1661} 1662 1663uint32_t
|
1604Gicv3CPUInterface::getHPPIR1()
|
1664Gicv3CPUInterface::getHPPIR1() const |
1665{ 1666 if (hppi.prio == 0xff) { 1667 return Gicv3::INTID_SPURIOUS; 1668 } 1669
|
1610 //if ((currEL() == EL3) && ICC_CTLR_EL3_RM)
1611 if ((currEL() == EL3) &&
1612 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3) & ICC_CTLR_EL3_RM) {
|
1670 ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1671 if ((currEL() == EL3) && icc_ctlr_el3.RM) { |
1672 if (hppi.group == Gicv3::G0S) { 1673 return Gicv3::INTID_SECURE; 1674 } else if (hppi.group == Gicv3::G1NS) { 1675 return Gicv3::INTID_NONSECURE; 1676 } 1677 } 1678 1679 if (hppi.group == Gicv3::G0S) { 1680 return Gicv3::INTID_SPURIOUS; 1681 } 1682 1683 bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 1684 1685 if (irq_is_secure) { 1686 if (!inSecureState()) { 1687 // Secure interrupts not visible in Non-secure 1688 return Gicv3::INTID_SPURIOUS; 1689 } 1690 } else if (!isEL3OrMon() && inSecureState()) { 1691 // Group 1 non-secure interrupts not visible in Secure EL1 1692 return Gicv3::INTID_SPURIOUS; 1693 } 1694 1695 return hppi.intid; 1696} 1697 1698void 1699Gicv3CPUInterface::dropPriority(Gicv3::GroupId group) 1700{ 1701 int apr_misc_reg; 1702 RegVal apr; 1703 apr_misc_reg = group == Gicv3::G0S ? 1704 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 1705 apr = isa->readMiscRegNoEffect(apr_misc_reg); 1706 1707 if (apr) {
|
1649 /* Clear the lowest set bit */
|
1708 apr &= apr - 1; 1709 isa->setMiscRegNoEffect(apr_misc_reg, apr); 1710 } 1711 1712 update(); 1713} 1714 1715uint8_t 1716Gicv3CPUInterface::virtualDropPriority() 1717{
|
1660 /* Drop the priority of the currently active virtual interrupt
1661 * (favouring group 0 if there is a set active bit at
1662 * the same priority for both group 0 and group 1).
1663 * Return the priority value for the bit we just cleared,
1664 * or 0xff if no bits were set in the AP registers at all.
1665 * Note that though the ich_apr[] are uint64_t only the low
1666 * 32 bits are actually relevant.
1667 */
|
1718 int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 1719 1720 for (int i = 0; i < apr_max; i++) { 1721 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 1722 RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 1723 1724 if (!vapr0 && !vapr1) { 1725 continue; 1726 } 1727 1728 int vapr0_count = ctz32(vapr0); 1729 int vapr1_count = ctz32(vapr1); 1730 1731 if (vapr0_count <= vapr1_count) {
|
1682 /* Clear the lowest set bit */
|
1732 vapr0 &= vapr0 - 1; 1733 isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 1734 return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 1735 } else {
|
1687 /* Clear the lowest set bit */
|
1736 vapr1 &= vapr1 - 1; 1737 isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 1738 return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 1739 } 1740 } 1741 1742 return 0xff; 1743} 1744 1745void 1746Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 1747{ 1748 // Update active priority registers. 1749 uint32_t prio = hppi.prio & 0xf8; 1750 int apr_bit = prio >> (8 - PRIORITY_BITS); 1751 int reg_bit = apr_bit % 32; 1752 int apr_idx = group == Gicv3::G0S ? 1753 MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 1754 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1755 apr |= (1 << reg_bit); 1756 isa->setMiscRegNoEffect(apr_idx, apr); 1757 1758 // Move interrupt state from pending to active. 1759 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1760 // SGI or PPI, redistributor 1761 redistributor->activateIRQ(int_id); 1762 redistributor->updateAndInformCPUInterface(); 1763 } else if (int_id < Gicv3::INTID_SECURE) { 1764 // SPI, distributor 1765 distributor->activateIRQ(int_id); 1766 distributor->updateAndInformCPUInterfaces(); 1767 } 1768} 1769 1770void 1771Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1772{ 1773 // Update active priority registers.
|
1726 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
|
1774 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + |
1775 lr_idx);
|
1728 Gicv3::GroupId group = lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
1729 uint8_t prio = bits(lr, 55, 48) & 0xf8;
|
1776 Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 1777 uint8_t prio = ich_lr_el.Priority & 0xf8; |
1778 int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 1779 int reg_no = apr_bit / 32; 1780 int reg_bit = apr_bit % 32; 1781 int apr_idx = group == Gicv3::G0S ? 1782 MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 1783 RegVal apr = isa->readMiscRegNoEffect(apr_idx); 1784 apr |= (1 << reg_bit); 1785 isa->setMiscRegNoEffect(apr_idx, apr); 1786 // Move interrupt state from pending to active.
|
1739 lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
1740 lr |= ICH_LR_EL2_STATE_ACTIVE_BIT;
1741 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, lr);
|
1787 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 1788 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); |
1789} 1790 1791void 1792Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 1793{ 1794 if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 1795 // SGI or PPI, redistributor 1796 redistributor->deactivateIRQ(int_id); 1797 redistributor->updateAndInformCPUInterface(); 1798 } else if (int_id < Gicv3::INTID_SECURE) { 1799 // SPI, distributor 1800 distributor->deactivateIRQ(int_id); 1801 distributor->updateAndInformCPUInterfaces(); 1802 } else { 1803 return; 1804 } 1805} 1806 1807void 1808Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 1809{
|
1763 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
|
1810 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + |
1811 lr_idx); 1812
|
1766 if (lr & ICH_LR_EL2_HW) {
|
1813 if (ich_lr_el2.HW) { |
1814 // Deactivate the associated physical interrupt
|
1768 int pintid = bits(lr, 41, 32);
1769
1770 if (pintid < Gicv3::INTID_SECURE) {
1771 Gicv3::GroupId group =
1772 pintid >= 32 ? distributor->getIntGroup(pintid) :
1773 redistributor->getIntGroup(pintid);
1774 deactivateIRQ(pintid, group);
|
1815 if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 1816 Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 1817 distributor->getIntGroup(ich_lr_el2.pINTID) : 1818 redistributor->getIntGroup(ich_lr_el2.pINTID); 1819 deactivateIRQ(ich_lr_el2.pINTID, group); |
1820 } 1821 } 1822 1823 // Remove the active bit
|
1779 lr &= ~ICH_LR_EL2_STATE_ACTIVE_BIT;
1780 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, lr);
|
1824 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 1825 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); |
1826} 1827 1828/*
|
1784 * Return a mask word which clears the subpriority bits from
1785 * a priority value for an interrupt in the specified group.
1786 * This depends on the BPR value. For CBPR0 (S or NS):
1787 * a BPR of 0 means the group priority bits are [7:1];
1788 * a BPR of 1 means they are [7:2], and so on down to
1789 * ...
1790 * a BPR of 7 meaning no group priority bits at all.
1791 * For CBPR1 NS:
1792 * a BPR of 0 is impossible (the minimum value is 1)
1793 * a BPR of 1 means the group priority bits are [7:1];
1794 * a BPR of 2 means they are [7:2], and so on down to
1795 * ...
1796 * a BPR of 7 meaning the group priority is [7].
1797 *
1798 * Which BPR to use depends on the group of the interrupt and
1799 * the current ICC_CTLR.CBPR settings.
1800 *
1801 * This corresponds to the GroupBits() pseudocode from 4.8.2.
|
1829 * Returns the priority group field for the current BPR value for the group. 1830 * GroupBits() Pseudocode from spec. |
1831 */ 1832uint32_t
|
1804Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
|
1833Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const |
1834{
|
1806 if ((group == Gicv3::G1S &&
1807 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
1808 & ICC_CTLR_EL1_CBPR) ||
1809 (group == Gicv3::G1NS &&
1810 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
1811 & ICC_CTLR_EL1_CBPR)) {
|
1835 ICC_CTLR_EL1 icc_ctlr_el1_s = 1836 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 1837 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1838 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 1839 1840 if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 1841 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { |
1842 group = Gicv3::G0S; 1843 } 1844 1845 int bpr; 1846 1847 if (group == Gicv3::G0S) { 1848 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7; 1849 } else { 1850 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7; 1851 } 1852 1853 if (group == Gicv3::G1NS) { 1854 assert(bpr > 0); 1855 bpr--; 1856 } 1857 1858 return ~0U << (bpr + 1); 1859} 1860 1861uint32_t
|
1832Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group)
|
1862Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const |
1863{
|
1834 RegVal ich_vmcr_el2 =
|
1864 ICH_VMCR_EL2 ich_vmcr_el2 = |
1865 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1866
|
1837 if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
|
1867 if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { |
1868 group = Gicv3::G0S; 1869 } 1870 1871 int bpr; 1872 1873 if (group == Gicv3::G0S) {
|
1844 bpr = bits(ich_vmcr_el2, 23, 21);
|
1874 bpr = ich_vmcr_el2.VBPR0; |
1875 } else {
|
1846 bpr = bits(ich_vmcr_el2, 20, 18);
|
1876 bpr = ich_vmcr_el2.VBPR1; |
1877 } 1878 1879 if (group == Gicv3::G1NS) { 1880 assert(bpr > 0); 1881 bpr--; 1882 } 1883 1884 return ~0U << (bpr + 1); 1885} 1886 1887bool
|
1858Gicv3CPUInterface::isEOISplitMode()
|
1888Gicv3CPUInterface::isEOISplitMode() const |
1889{ 1890 if (isEL3OrMon()) {
|
1861 return isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3) &
1862 ICC_CTLR_EL3_EOIMODE_EL3;
|
1891 ICC_CTLR_EL3 icc_ctlr_el3 = 1892 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 1893 return icc_ctlr_el3.EOImode_EL3; |
1894 } else {
|
1864 return isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1) &
1865 ICC_CTLR_EL1_EOIMODE;
|
1895 ICC_CTLR_EL1 icc_ctlr_el1 = 1896 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 1897 return icc_ctlr_el1.EOImode; |
1898 } 1899} 1900 1901bool
|
1870Gicv3CPUInterface::virtualIsEOISplitMode()
|
1902Gicv3CPUInterface::virtualIsEOISplitMode() const |
1903{
|
1872 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
1873 return ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
|
1904 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 1905 return ich_vmcr_el2.VEOIM; |
1906} 1907 1908int
|
1877Gicv3CPUInterface::highestActiveGroup()
|
1909Gicv3CPUInterface::highestActiveGroup() const |
1910{ 1911 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 1912 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 1913 int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 1914 1915 if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 1916 return Gicv3::G1NS; 1917 } 1918 1919 if (gq_ctz < g0_ctz) { 1920 return Gicv3::G1S; 1921 } 1922 1923 if (g0_ctz < 32) { 1924 return Gicv3::G0S; 1925 } 1926 1927 return -1; 1928} 1929 1930void 1931Gicv3CPUInterface::update() 1932{ 1933 bool signal_IRQ = false; 1934 bool signal_FIQ = false; 1935 1936 if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 1937 /* 1938 * Secure enabled GIC sending a G1S IRQ to a secure disabled 1939 * CPU -> send G0 IRQ 1940 */ 1941 hppi.group = Gicv3::G0S; 1942 } 1943 1944 if (hppiCanPreempt()) { 1945 ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 1946 DPRINTF(GIC, "Gicv3CPUInterface::update(): " 1947 "posting int as %d!\n", int_type); 1948 int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 1949 } 1950 1951 if (signal_IRQ) { 1952 gic->postInt(cpuId, ArmISA::INT_IRQ); 1953 } else { 1954 gic->deassertInt(cpuId, ArmISA::INT_IRQ); 1955 } 1956 1957 if (signal_FIQ) { 1958 gic->postInt(cpuId, ArmISA::INT_FIQ); 1959 } else { 1960 gic->deassertInt(cpuId, ArmISA::INT_FIQ); 1961 } 1962} 1963 1964void 1965Gicv3CPUInterface::virtualUpdate() 1966{ 1967 bool signal_IRQ = false; 1968 bool signal_FIQ = false; 1969 int lr_idx = getHPPVILR(); 1970 1971 if (lr_idx >= 0) {
|
1940 RegVal ich_lr_el2 =
|
1972 ICH_LR_EL2 ich_lr_el2 = |
1973 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 1974 1975 if (hppviCanPreempt(lr_idx)) {
|
1944 if (ich_lr_el2 & ICH_LR_EL2_GROUP) {
|
1976 if (ich_lr_el2.Group) { |
1977 signal_IRQ = true; 1978 } else { 1979 signal_FIQ = true; 1980 } 1981 } 1982 } 1983
|
1952 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
|
1984 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); |
1985
|
1954 if (ich_hcr_el2 & ICH_HCR_EL2_EN) {
|
1986 if (ich_hcr_el2.En) { |
1987 if (maintenanceInterruptStatus()) { 1988 redistributor->sendPPInt(25); 1989 } 1990 } 1991 1992 if (signal_IRQ) { 1993 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 1994 "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 1995 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 1996 } else { 1997 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 1998 } 1999 2000 if (signal_FIQ) { 2001 DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 2002 "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 2003 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 2004 } else { 2005 gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 2006 } 2007} 2008
|
1977// Returns the intex of the LR with the HPPI
|
2009// Returns the index of the LR with the HPPI |
2010int
|
1979Gicv3CPUInterface::getHPPVILR()
|
2011Gicv3CPUInterface::getHPPVILR() const |
2012{ 2013 int idx = -1;
|
1982 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
|
2014 ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); |
2015
|
1984 if (!(ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
|
2016 if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { |
2017 // VG0 and VG1 disabled... 2018 return idx; 2019 } 2020 2021 uint8_t highest_prio = 0xff; 2022 2023 for (int i = 0; i < 16; i++) {
|
1992 RegVal ich_lri_el2 =
|
2024 ICH_LR_EL2 ich_lr_el2 = |
2025 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
|
1994 uint8_t state = bits(ich_lri_el2, 63, 62);
|
2026
|
1996 if (state != Gicv3::INT_PENDING) {
|
2027 if (ich_lr_el2.State != Gicv3::INT_PENDING) { |
2028 continue; 2029 } 2030
|
2000 if (ich_lri_el2 & ICH_LR_EL2_GROUP) {
|
2031 if (ich_lr_el2.Group) { |
2032 // VG1
|
2002 if (!(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
|
2033 if (!ich_vmcr_el2.VENG1) { |
2034 continue; 2035 } 2036 } else { 2037 // VG0
|
2007 if (!(ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
|
2038 if (!ich_vmcr_el2.VENG0) { |
2039 continue; 2040 } 2041 } 2042
|
2012 uint8_t prio = bits(ich_lri_el2, 55, 48);
|
2043 uint8_t prio = ich_lr_el2.Priority; |
2044 2045 if (prio < highest_prio) { 2046 highest_prio = prio; 2047 idx = i; 2048 } 2049 } 2050 2051 return idx; 2052} 2053 2054bool
|
2024Gicv3CPUInterface::hppviCanPreempt(int lr_idx)
|
2055Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const |
2056{
|
2026 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2027
2028 if (!(isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2) & ICH_HCR_EL2_EN)) {
|
2057 ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2058 if (!ich_hcr_el2.En) { |
2059 // virtual interface is disabled 2060 return false; 2061 } 2062
|
2033 uint8_t prio = bits(lr, 55, 48);
|
2063 ICH_LR_EL2 ich_lr_el2 = 2064 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 2065 uint8_t prio = ich_lr_el2.Priority; |
2066 uint8_t vpmr = 2067 bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 2068 2069 if (prio >= vpmr) { 2070 // prioriry masked 2071 return false; 2072 } 2073 2074 uint8_t rprio = virtualHighestActivePriority(); 2075 2076 if (rprio == 0xff) { 2077 return true; 2078 } 2079
|
2048 Gicv3::GroupId group = lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
|
2080 Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; |
2081 uint32_t prio_mask = virtualGroupPriorityMask(group); 2082 2083 if ((prio & prio_mask) < (rprio & prio_mask)) { 2084 return true; 2085 } 2086 2087 return false; 2088} 2089 2090uint8_t
|
2059Gicv3CPUInterface::virtualHighestActivePriority()
|
2091Gicv3CPUInterface::virtualHighestActivePriority() const |
2092{ 2093 uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 2094 2095 for (int i = 0; i < num_aprs; i++) { 2096 RegVal vapr = 2097 isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 2098 isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 2099 2100 if (!vapr) { 2101 continue; 2102 } 2103 2104 return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 2105 } 2106 2107 // no active interrups, return idle priority 2108 return 0xff; 2109} 2110 2111void 2112Gicv3CPUInterface::virtualIncrementEOICount() 2113{ 2114 // Increment the EOICOUNT field in ICH_HCR_EL2 2115 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2116 uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 2117 EOI_cout++; 2118 ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 2119 isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 2120} 2121
|
2090/*
2091 * Should we signal the interrupt as IRQ or FIQ?
2092 * see spec section 4.6.2
2093 */
|
2122// spec section 4.6.2 |
2123ArmISA::InterruptTypes
|
2095Gicv3CPUInterface::intSignalType(Gicv3::GroupId group)
|
2124Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const |
2125{ 2126 bool is_fiq = false; 2127 2128 switch (group) { 2129 case Gicv3::G0S: 2130 is_fiq = true; 2131 break; 2132 2133 case Gicv3::G1S: 2134 is_fiq = (distributor->DS == 0) && 2135 (!inSecureState() || ((currEL() == EL3) && isAA64())); 2136 break; 2137 2138 case Gicv3::G1NS: 2139 is_fiq = (distributor->DS == 0) && inSecureState(); 2140 break; 2141 2142 default: 2143 panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 2144 } 2145 2146 if (is_fiq) { 2147 return ArmISA::INT_FIQ; 2148 } else { 2149 return ArmISA::INT_IRQ; 2150 } 2151} 2152 2153bool
|
2125Gicv3CPUInterface::hppiCanPreempt()
|
2154Gicv3CPUInterface::hppiCanPreempt() const |
2155{ 2156 if (hppi.prio == 0xff) { 2157 // there is no pending interrupt 2158 return false; 2159 } 2160 2161 if (!groupEnabled(hppi.group)) { 2162 // group disabled at CPU interface 2163 return false; 2164 } 2165 2166 if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 2167 // priority masked 2168 return false; 2169 } 2170 2171 uint8_t rprio = highestActivePriority(); 2172 2173 if (rprio == 0xff) { 2174 return true; 2175 } 2176 2177 uint32_t prio_mask = groupPriorityMask(hppi.group); 2178 2179 if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 2180 return true; 2181 } 2182 2183 return false; 2184} 2185 2186uint8_t
|
2158Gicv3CPUInterface::highestActivePriority()
|
2187Gicv3CPUInterface::highestActivePriority() const |
2188{ 2189 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 2190 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 2191 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 2192 2193 if (apr) { 2194 return ctz32(apr) << (GIC_MIN_BPR + 1); 2195 } 2196 2197 // no active interrups, return idle priority 2198 return 0xff; 2199} 2200 2201bool
|
2173Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group)
|
2202Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const |
2203{ 2204 switch (group) {
|
2176 case Gicv3::G0S:
2177 return isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1) &
2178 ICC_IGRPEN0_EL1_ENABLE;
|
2205 case Gicv3::G0S: { 2206 ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 2207 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 2208 return icc_igrpen0_el1.Enable; 2209 } |
2210
|
2180 case Gicv3::G1S:
2181 //if (distributor->DS)
2182 //{
2183 // return isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS) &
2184 // ICC_IGRPEN1_EL1_ENABLE;
2185 //}
2186 //else
2187 //{
2188 return isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S) &
2189 ICC_IGRPEN1_EL1_ENABLE;
|
2211 case Gicv3::G1S: { 2212 ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 2213 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 2214 return icc_igrpen1_el1_s.Enable; 2215 } |
2216
|
2191 //}
|
2217 case Gicv3::G1NS: { 2218 ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 2219 isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 2220 return icc_igrpen1_el1_ns.Enable; 2221 } |
2222
|
2193 case Gicv3::G1NS:
2194 return isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS) &
2195 ICC_IGRPEN1_EL1_ENABLE;
2196
|
2223 default: 2224 panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 2225 } 2226} 2227 2228bool
|
2203Gicv3CPUInterface::inSecureState()
|
2229Gicv3CPUInterface::inSecureState() const |
2230{ 2231 if (!gic->getSystem()->haveSecurity()) { 2232 return false; 2233 } 2234 2235 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2236 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 2237 return ArmISA::inSecureState(scr, cpsr); 2238} 2239 2240int
|
2215Gicv3CPUInterface::currEL()
|
2241Gicv3CPUInterface::currEL() const |
2242{ 2243 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2244 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2245 2246 if (is_64) { 2247 return (ExceptionLevel)(uint8_t) cpsr.el; 2248 } else { 2249 switch (cpsr.mode) { 2250 case MODE_USER: 2251 return 0; 2252 2253 case MODE_HYP: 2254 return 2; 2255 2256 case MODE_MON: 2257 return 3; 2258 2259 default: 2260 return 1; 2261 } 2262 } 2263} 2264 2265bool
|
2240Gicv3CPUInterface::haveEL(ExceptionLevel el)
|
2266Gicv3CPUInterface::haveEL(ExceptionLevel el) const |
2267{ 2268 switch (el) { 2269 case EL0: 2270 case EL1: 2271 return true; 2272 2273 case EL2: 2274 return gic->getSystem()->haveVirtualization(); 2275 2276 case EL3: 2277 return gic->getSystem()->haveSecurity(); 2278 2279 default: 2280 warn("Unimplemented Exception Level\n"); 2281 return false; 2282 } 2283} 2284 2285bool
|
2260Gicv3CPUInterface::isSecureBelowEL3()
|
2286Gicv3CPUInterface::isSecureBelowEL3() const |
2287{ 2288 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 2289 return haveEL(EL3) && scr.ns == 0; 2290} 2291 2292bool
|
2267Gicv3CPUInterface::isAA64()
|
2293Gicv3CPUInterface::isAA64() const |
2294{ 2295 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2296 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2297} 2298 2299bool
|
2274Gicv3CPUInterface::isEL3OrMon()
|
2300Gicv3CPUInterface::isEL3OrMon() const |
2301{ 2302 if (haveEL(EL3)) { 2303 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 2304 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 2305 2306 if (is_64 && (cpsr.el == EL3)) { 2307 return true; 2308 } else if (!is_64 && (cpsr.mode == MODE_MON)) { 2309 return true; 2310 } 2311 } 2312 2313 return false; 2314} 2315
|
2290uint32_t
2291Gicv3CPUInterface::eoiMaintenanceInterruptStatus(uint32_t * misr)
|
2316// Computes ICH_EISR_EL2 2317uint64_t 2318Gicv3CPUInterface::eoiMaintenanceInterruptStatus() const |
2319{
|
2293 /* Return a set of bits indicating the EOI maintenance interrupt status
2294 * for each list register. The EOI maintenance interrupt status is
2295 * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1
2296 * (see the GICv3 spec for the ICH_EISR_EL2 register).
2297 * If misr is not NULL then we should also collect the information
2298 * about the MISR.EOI, MISR.NP and MISR.U bits.
2299 */
2300 uint32_t value = 0;
2301 int valid_count = 0;
2302 bool seen_pending = false;
|
2320 // ICH_EISR_EL2 2321 // Bits [63:16] - RES0 2322 // Status<n>, bit [n], for n = 0 to 15 2323 // EOI maintenance interrupt status bit for List register <n>: 2324 // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 2325 // maintenance interrupt. 2326 // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 2327 // interrupt that has not been handled. 2328 // 2329 // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 2330 // of the following are true: 2331 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 2332 // - ICH_LR<n>_EL2.HW is 0. 2333 // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. |
2334
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2335 uint64_t value = 0; 2336 |
2337 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
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2305 RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
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2338 ICH_LR_EL2 ich_lr_el2 = 2339 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); |
2340
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2307 if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) ==
2308 ICH_LR_EL2_EOI) {
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2341 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 2342 !ich_lr_el2.HW && ich_lr_el2.EOI) { |
2343 value |= (1 << lr_idx); 2344 }
|
2345 } |
2346
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2312 if ((lr & ICH_LR_EL2_STATE_MASK)) {
2313 valid_count++;
2314 }
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2347 return value; 2348} |
2349
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2316 if (bits(lr, ICH_LR_EL2_STATE_SHIFT + ICH_LR_EL2_STATE_LENGTH,
2317 ICH_LR_EL2_STATE_SHIFT) == ICH_LR_EL2_STATE_PENDING) {
2318 seen_pending = true;
2319 }
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2350Gicv3CPUInterface::ICH_MISR_EL2 2351Gicv3CPUInterface::maintenanceInterruptStatus() const 2352{ 2353 // Comments are copied from SPEC section 9.4.7 (ID012119) 2354 ICH_MISR_EL2 ich_misr_el2 = 0; 2355 ICH_HCR_EL2 ich_hcr_el2 = 2356 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 2357 ICH_VMCR_EL2 ich_vmcr_el2 = 2358 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 2359 2360 // End Of Interrupt. [bit 0] 2361 // This maintenance interrupt is asserted when at least one bit in 2362 // ICH_EISR_EL2 is 1. 2363 2364 if (eoiMaintenanceInterruptStatus()) { 2365 ich_misr_el2.EOI = 1; |
2366 } 2367
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2322 if (misr) {
2323 RegVal ich_hcr_el2 =
2324 isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
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2368 // Underflow. [bit 1] 2369 // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 2370 // zero or one of the List register entries are marked as a valid 2371 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 2372 // do not equal 0x0. 2373 uint32_t num_valid_interrupts = 0; 2374 uint32_t num_pending_interrupts = 0; |
2375
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2326 if (valid_count < 2 && (ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
2327 *misr |= ICH_MISR_EL2_U;
2328 }
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2376 for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 2377 ICH_LR_EL2 ich_lr_el2 = 2378 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); |
2379
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2330 if (!seen_pending && (ich_hcr_el2 & ICH_HCR_EL2_NPIE)) {
2331 *misr |= ICH_MISR_EL2_NP;
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2380 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 2381 num_valid_interrupts++; |
2382 } 2383
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2334 if (value) {
2335 *misr |= ICH_MISR_EL2_EOI;
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2384 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 2385 num_pending_interrupts++; |
2386 } 2387 } 2388
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2339 return value;
2340}
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2389 if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 2390 ich_misr_el2.U = 1; 2391 } |
2392
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2342uint32_t
2343Gicv3CPUInterface::maintenanceInterruptStatus()
2344{
2345 /* Return a set of bits indicating the maintenance interrupt status
2346 * (as seen in the ICH_MISR_EL2 register).
2347 */
2348 uint32_t value = 0;
2349 /* Scan list registers and fill in the U, NP and EOI bits */
2350 eoiMaintenanceInterruptStatus(&value);
2351 RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
2352 RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
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2393 // List Register Entry Not Present. [bit 2] 2394 // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 2395 // and ICH_HCR_EL2.EOIcount is non-zero. 2396 if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 2397 ich_misr_el2.LRENP = 1; 2398 } |
2399
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2354 if (ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
2355 value |= ICH_MISR_EL2_LRENP;
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2400 // No Pending. [bit 3] 2401 // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 2402 // no List register is in pending state. 2403 if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 2404 ich_misr_el2.NP = 1; |
2405 } 2406
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2358 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
2359 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
2360 value |= ICH_MISR_EL2_VGRP0E;
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2407 // vPE Group 0 Enabled. [bit 4] 2408 // This maintenance interrupt is asserted when 2409 // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 2410 if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 2411 ich_misr_el2.VGrp0E = 1; |
2412 } 2413
|
2363 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
2364 !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
2365 value |= ICH_MISR_EL2_VGRP0D;
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2414 // vPE Group 0 Disabled. [bit 5] 2415 // This maintenance interrupt is asserted when 2416 // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 2417 if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 2418 ich_misr_el2.VGrp0D = 1; |
2419 } 2420
|
2368 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
2369 (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
2370 value |= ICH_MISR_EL2_VGRP1E;
|
2421 // vPE Group 1 Enabled. [bit 6] 2422 // This maintenance interrupt is asserted when 2423 // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 2424 if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 2425 ich_misr_el2.VGrp1E = 1; |
2426 } 2427
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2373 if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
2374 !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
2375 value |= ICH_MISR_EL2_VGRP1D;
|
2428 // vPE Group 1 Disabled. [bit 7] 2429 // This maintenance interrupt is asserted when 2430 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 2431 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 2432 ich_misr_el2.VGrp1D = 1; |
2433 } 2434
|
2378 return value;
|
2435 return ich_misr_el2; |
2436} 2437 2438void 2439Gicv3CPUInterface::serialize(CheckpointOut & cp) const 2440{ 2441 SERIALIZE_SCALAR(hppi.intid); 2442 SERIALIZE_SCALAR(hppi.prio); 2443 SERIALIZE_ENUM(hppi.group); 2444} 2445 2446void 2447Gicv3CPUInterface::unserialize(CheckpointIn & cp) 2448{ 2449 UNSERIALIZE_SCALAR(hppi.intid); 2450 UNSERIALIZE_SCALAR(hppi.prio); 2451 UNSERIALIZE_ENUM(hppi.group); 2452}
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