1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 56 unchanged lines hidden (view full) --- 65void 66Gicv3CPUInterface::init() 67{ 68 redistributor = gic->getRedistributor(cpuId); 69 distributor = gic->getDistributor(); 70} 71 72void |
73Gicv3CPUInterface::resetHppi(uint32_t intid) 74{ 75 if (intid == hppi.intid) 76 hppi.prio = 0xff; 77} 78 79void |
80Gicv3CPUInterface::setThreadContext(ThreadContext *tc) 81{ 82 maintenanceInterrupt = gic->params()->maint_int->get(tc); 83} 84 85bool 86Gicv3CPUInterface::getHCREL2FMO() const 87{ --- 1757 unchanged lines hidden (view full) --- 1845 } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 1846 // LPI, Redistributor 1847 redistributor->setClrLPI(int_id, false); 1848 } 1849 1850 // By setting the priority to 0xff we are effectively 1851 // making the int_id not pending anymore at the cpu 1852 // interface. |
1853 resetHppi(int_id); |
1854 updateDistributor(); 1855} 1856 1857void 1858Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 1859{ 1860 // Update active priority registers. 1861 ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + --- 728 unchanged lines hidden --- |