1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 290 unchanged lines hidden (view full) --- 299 } 300 } 301 302 break; 303 } 304 305 // Binary Point Register 0 306 case MISCREG_ICC_BPR0: |
307 case MISCREG_ICC_BPR0_EL1: { |
308 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 309 return readMiscReg(MISCREG_ICV_BPR0_EL1); 310 } 311 |
312 value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 313 break; 314 } |
315 316 // Binary Point Register 1 317 case MISCREG_ICC_BPR1: 318 case MISCREG_ICC_BPR1_EL1: { |
319 value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS); 320 break; 321 } |
322 |
323 // Virtual Binary Point Register 0 324 case MISCREG_ICV_BPR0_EL1: { 325 ICH_VMCR_EL2 ich_vmcr_el2 = 326 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); |
327 |
328 value = ich_vmcr_el2.VBPR0; 329 break; |
330 } 331 332 // Virtual Binary Point Register 1 |
333 case MISCREG_ICV_BPR1_EL1: { |
334 ICH_VMCR_EL2 ich_vmcr_el2 = 335 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); |
336 |
337 if (ich_vmcr_el2.VCBPR) { 338 // bpr0 + 1 saturated to 7, WI 339 value = ich_vmcr_el2.VBPR0 + 1; 340 value = value < 7 ? value : 7; 341 } else { 342 value = ich_vmcr_el2.VBPR1; 343 } |
344 |
345 break; |
346 } 347 348 // Interrupt Priority Mask Register 349 case MISCREG_ICC_PMR: 350 case MISCREG_ICC_PMR_EL1: 351 if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 352 return readMiscReg(MISCREG_ICV_PMR_EL1); 353 } --- 677 unchanged lines hidden (view full) --- 1031 } 1032 1033 virtualUpdate(); 1034 break; 1035 } 1036 1037 // Binary Point Register 0 1038 case MISCREG_ICC_BPR0: |
1039 case MISCREG_ICC_BPR0_EL1: { 1040 if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 1041 return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 1042 } 1043 break; 1044 } |
1045 // Binary Point Register 1 1046 case MISCREG_ICC_BPR1: 1047 case MISCREG_ICC_BPR1_EL1: { |
1048 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 1049 return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 1050 } |
1051 |
1052 val &= 0x7; |
1053 |
1054 if (isSecureBelowEL3()) { 1055 // group == Gicv3::G1S 1056 ICC_CTLR_EL1 icc_ctlr_el1_s = 1057 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); |
1058 |
1059 val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR; 1060 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 1061 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val); 1062 } else { 1063 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val); 1064 } 1065 return; 1066 } else { 1067 // group == Gicv3::G1NS 1068 ICC_CTLR_EL1 icc_ctlr_el1_ns = 1069 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); |
1070 |
1071 val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS; 1072 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 1073 // Non secure writes from EL1 and EL2 are ignored 1074 } else { 1075 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val); 1076 } 1077 return; 1078 } |
1079 |
1080 break; |
1081 } 1082 1083 // Virtual Binary Point Register 0 1084 case MISCREG_ICV_BPR0_EL1: 1085 // Virtual Binary Point Register 1 1086 case MISCREG_ICV_BPR1_EL1: { 1087 Gicv3::GroupId group = 1088 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; --- 807 unchanged lines hidden (view full) --- 1896 (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 1897 group = Gicv3::G0S; 1898 } 1899 1900 int bpr; 1901 1902 if (group == Gicv3::G0S) { 1903 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; |
1904 } else if (group == Gicv3::G1S) { 1905 bpr = bpr1(Gicv3::G1S) & 0x7; |
1906 } else { |
1907 bpr = bpr1(Gicv3::G1NS) & 0x7; |
1908 } 1909 1910 if (group == Gicv3::G1NS) { 1911 assert(bpr > 0); 1912 bpr--; 1913 } 1914 1915 return ~0U << (bpr + 1); --- 577 unchanged lines hidden (view full) --- 2493 // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 2494 if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 2495 ich_misr_el2.VGrp1D = 1; 2496 } 2497 2498 return ich_misr_el2; 2499} 2500 |
2501RegVal 2502Gicv3CPUInterface::bpr1(Gicv3::GroupId group) 2503{ 2504 bool hcr_imo = getHCREL2IMO(); 2505 if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 2506 return readMiscReg(MISCREG_ICV_BPR1_EL1); 2507 } 2508 2509 RegVal bpr = 0; 2510 2511 if (group == Gicv3::G1S) { 2512 ICC_CTLR_EL1 icc_ctlr_el1_s = 2513 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 2514 2515 if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 2516 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 2517 } else { 2518 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S); 2519 bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR; 2520 } 2521 } else if (group == Gicv3::G1NS) { 2522 ICC_CTLR_EL1 icc_ctlr_el1_ns = 2523 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 2524 2525 // Check if EL3 is implemented and this is a non secure accesses at 2526 // EL1 and EL2 2527 if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 2528 // Reads return BPR0 + 1 saturated to 7, WI 2529 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1; 2530 bpr = bpr < 7 ? bpr : 7; 2531 } else { 2532 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS); 2533 bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS; 2534 } 2535 } else { 2536 panic("Should be used with G1S and G1NS only\n"); 2537 } 2538 2539 return bpr; 2540} 2541 |
2542void 2543Gicv3CPUInterface::serialize(CheckpointOut & cp) const 2544{ 2545 SERIALIZE_SCALAR(hppi.intid); 2546 SERIALIZE_SCALAR(hppi.prio); 2547 SERIALIZE_ENUM(hppi.group); 2548} 2549 2550void 2551Gicv3CPUInterface::unserialize(CheckpointIn & cp) 2552{ 2553 UNSERIALIZE_SCALAR(hppi.intid); 2554 UNSERIALIZE_SCALAR(hppi.prio); 2555 UNSERIALIZE_ENUM(hppi.group); 2556} |